beginner: programmable counter designed by CPLD/FPGA?

[sunyixiang]

I need to design 8 independent programmable counters by using CPLD or FPGA on a VMEbus slave. The clock frequency to these counters is 160 MHz and their N counts are programmable between 4000 to 5300. The outputs of 8 channels should be square waves with 30 - 40 kHz.

I want to design these counters by using CPLD or FPGA, is it resonable? Or you have a better idea?

If I can or have to use CPLD or FPGA, which one is better? What device do I choose? What development kit do I choose?

I am a beginner and don't know how and where I begin this project. Thanks a lot.

 

[alvinus]

if u have FPGA, of course go with FPGA since can hold more gates etc
i think any FPGA development kit will do right? for me, my col only provides altera up2 boards
u need to use HDL codes to do or only with logic gates?

 

[echo47]

I use various Xilinx FPGAs, so I recommend the inexpensive Spartan-3 FPGA. Even the smallest one has over 1500 flip-flops, plenty to build a few programmable counters. 160 MHz is fine.

You can buy the Spartan 3 Starter Kit from either Xilinx or Digilent. Digilent offers kits with different-size FPGAs, but I think you have to download the development software from Xilinx (it's free but huge). The Xilinx kit includes CD-ROMs.
**broken link removed**
http://www.digilentinc.com/info/S3Board.cfm

If you have never used FPGAs, beware of a steep learning curve. You will want to learn Verilog or VHDL, because it's a lot easier than schematic entry.

If your project can wait a little while, also consider the new Spartan-3E. Several nice improvements including new simpler configuration methods.

I don't know anything about VMEbus, but beware that most modern FPGAs don't interface directly to 5V logic.