[SOLVED] ATPG tool that takes transistor level spice netlist as an input.

[dhaval4987]

I need an ATPG tool to generate delay fault test vectors but I have transistor level spice netlist and transistor BSIM 4 model, I need to use these files as an input.

I found out that Tetramax is a good tool but it only takes HDL netlist. Is there any tool which uses the spice netlist as an input?

 

[dhaval4987]

After doing quite a bit research- I found that there is no commercial tool that does this. All ATPG work at boolean logic level. Research is going on to make it work at transistor level but no commercial tools.

Closing this thread. If anyone finds out any tool that works with transistor level spice netlist- let me know by private message and I will re-open this thread to share with all!

Thanks.