skamthey
Member level 3
ATPG Help...
HI everyone,
I want to generate test patterns (in TetraMax ) for an And-Or logic(gate level) which is designed using VHDL or Verilog.:?:
How can i do this.
Will it require Design Compiler somewhere in the flow.
It will be helpful if i come to know step by step procedure.
HI everyone,
I want to generate test patterns (in TetraMax ) for an And-Or logic(gate level) which is designed using VHDL or Verilog.:?:
How can i do this.
Will it require Design Compiler somewhere in the flow.
It will be helpful if i come to know step by step procedure.