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ATPG Help... generate test patterns (in TetraMax )

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skamthey

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ATPG Help...

HI everyone,
I want to generate test patterns (in TetraMax ) for an And-Or logic(gate level) which is designed using VHDL or Verilog.:?:
How can i do this.
Will it require Design Compiler somewhere in the flow.
It will be helpful if i come to know step by step procedure.
 

santhosh007

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ATPG Help...

i cant generate a patterns for the combinational logic... you need to have some scan flops too.
 

skyismylimit

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Re: ATPG Help...

Do u really need tetramax to generate pattern for and-or logic.. I think you can work out yourself thinking about the stuck at faults at each node.. You surely require some flops in the scan chain to do the tetramax..
 

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