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ATPG ATE test - failure occurs after 35 patterns

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Junior Member level 1
May 27, 2009
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help on ATPG ATE test!

Hi, everyone,

I generated ATPG patterns using Mentor's Fastscan and simulated with sdf back-annotation. But the test engineer could not get the patterns passed on ATE. And the first fail happens to the 36th pattern (serial) which means the first 35 patterns are fine.

1. Is that normal?
2. Why changing the scan clk freq/probe time does not help?

Thanks a lot!!

Re: help on ATPG ATE test!

Nobody can help?

I'm not a testing engineer...

help on ATPG ATE test!

Are you simulating a parallel testbench or a serial testbench? Have you run STA?

help on ATPG ATE test!

There are a number of possible causes. A lot of these stem out of timing relationships between flops. Since you have managed to pass 35 patterns, we can assume timing for shifting is no problem. So if there is any timing problems, it will have to be on the capture cycle. How many clock domains do you have? Did you do STA for scan? How is your clocking scheme during scan tests? etc.

One other possibility is the presence of blocks that are not pure digital logic like analog blocks, memories, etc. How did you deal with these? Did you have a wrapper around them? Did you create an ATPG model? If so, how does this relate to the real block on silicon? etc.

Post more info and maybe I or some other people here can help you walk though it.

help on ATPG ATE test!

I have meet same question before, a false path signal trans into scan, at normal condition it work well, at worst condition the pattern fail , And what you pattern stuck-at , transition?

Re: help on ATPG ATE test!

Thanks a lot to all!

1. I have only one clk domain, cause all the internal generated clks have been muxed by scan_mode signal;

2. I did stuck-at fault ATPG;

3. Before delivered the patterns, I have ran all the parallel patterns and three serial patterns. All passed for SS/TT/FF corners;

4. STA has been done successfully;

5. All the analog blocks and memories have been black-boxed. And during the pattern generation, I have put PLL in sleep mode/disabled MBIST;

6. If there is a false path, the PT should be able to catch it, right? But I was told that the STA passed.

Thanks again for all your replies!

help on ATPG ATE test!

I think false path sometimes may cause error. Some false path is control by register or mux, when do atpg the register is caculate by atpg tools, if the mux control is wrong , the path may not be a false path.
When do sta , we tell the tools the path is false path, sta tools will not caculate the false path timing.

help on ATPG ATE test!

I would double check your STA scripts & then make sure your analog models are accurate or better yet pessimistic (e.g. all analog outputs 'x' during scan mode)

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