Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

asynchronous timing arc characrterization

Status
Not open for further replies.
N

nitin kala

Junior Member level 1
Junior Member level 1
Joined
Apr 17, 2010
Messages
15
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Location
Hyderabad
Activity points
1,347
Hi all,

While doing removal & recovery time characterization for 45nm library, i find erroneous results for high clock pin & CDN/SDN pin transition time.
Please suggest me what measures can be taken for characterizing flops with higher transition times values of clock signal
or asynchronous signals ( reset/clear ).

Regards,
Nitin
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top