Why doesn't clock transition time affect my timing analysis (PrimeTime)?

[EE18]

I am simulating the circuit attached with cells from the lsi_10k.lib built-in library (provided with Design Compiler/PrimeTime) and have enforced the constraints below:

#-----------------------------------------------#
# ENFORCE CONSTRAINTS
#-----------------------------------------------#
# Define clock plus its natural latency
create_clock -name CLK -period 10 [get_ports Clock]
set_propagated_clock [get_clocks CLK]
set_clock_uncertainty 1 -hold [get_clocks CLK]
set_clock_uncertainty 1 -setup [get_clocks CLK]
set_clock_latency 1 -source [get_clocks CLK]
set_clock_transition 2 [get_clocks CLK]
set_input_delay -clock CLK 2 [all_inputs]
set_output_delay -clock CLK 2 [all_outputs]

As you can see, I do have a set_clock_transition command. Nevertheless, there is zero dependence on the value I provide there (whether 0 or very large). Why is this? I expect delay through the inverters (at least the first one on the path! In the report below this is the I1/Z (IVA) cell delay of 0.49 time units) to slow down, but this is not observed. The lsi_10k.lib library does seem to have enough information about the relevant cells that a delay calculator should compute different delays in different slew rate situations too, I think?

Setup analysis output:

****************************************
Report : timing
-path_type full_clock_expanded
-delay_type max
-slack_lesser_than 1000000.00
-max_paths 1
-sort_by slack
Design : MyComp
Version: T-2022.03
Date : Tue Aug 13 21:44:09 2024
****************************************


Startpoint: F3 (rising edge-triggered flip-flop clocked by CLK)
Endpoint: OUT (output port clocked by CLK)
Path Group: CLK
Path Type: max

Point Incr Path
---------------------------------------------------------------
clock CLK (rise edge) 0.00 0.00
clock source latency 1.00 1.00
Clock (in) 0.00 1.00 r
I1/Z (IVA) 0.49 1.49 f
I4/Z (IV) 0.67 2.15 r
I5/Z (IVP) 0.21 2.36 f
I6/Z (IVA) 0.31 2.68 r
F3/CP (FD1) 0.00 2.68 r
F3/Q (FD1) 1.37 4.05 f
OUT (out) 0.00 4.05 f
data arrival time 4.05

clock CLK (rise edge) 10.00 10.00
clock network delay (propagated) 1.00 11.00
clock reconvergence pessimism 0.00 11.00
clock uncertainty -1.00 10.00
output external delay -2.00 8.00
data required time 8.00
---------------------------------------------------------------
data required time 8.00
data arrival time -4.05
---------------------------------------------------------------
slack (MET) 3.95


1

Can anyone set me straight on what I'm missing?

 

[glennramalho]

It might be something simple. I would check a few things. First, what is the unit. The liberty file usually specifies a default unit but it might be very small. Perhaps you are doing a rise time in picoseconds. Try, for example, set_units -time ns.

Is this pre or post P&R? Perhaps there is something wrong with the wire-load model being used.
Or maybe it is post P&R and then the clock is set to ideal. An ideal clock arrives at all places instantly. I bet it ignores the rise/fall time with ideal clocks. Maybe you need to do: set_propagated_clock [all_clocks]

And finally I would make sure you are really loading the right file. Sounds like a dumb mistake but it happens. I have spent long time changing one file and wondering why it has no impact and finding out I was loading a different file. Often when you make changes to a file and you see no impact it is a sign you are changing the wrong file. As a sanity I occasionally will add a typo to the file and load it to see if I see the syntax error. A simple way to make sure I am changing the right file.

 

[EE18]

It might be something simple. I would check a few things. First, what is the unit. The liberty file usually specifies a default unit but it might be very small. Perhaps you are doing a rise time in picoseconds. Try, for example, set_units -time ns.

Is this pre or post P&R? Perhaps there is something wrong with the wire-load model being used.
Or maybe it is post P&R and then the clock is set to ideal. An ideal clock arrives at all places instantly. I bet it ignores the rise/fall time with ideal clocks. Maybe you need to do: set_propagated_clock [all_clocks]

And finally I would make sure you are really loading the right file. Sounds like a dumb mistake but it happens. I have spent long time changing one file and wondering why it has no impact and finding out I was loading a different file. Often when you make changes to a file and you see no impact it is a sign you are changing the wrong file. As a sanity I occasionally will add a typo to the file and load it to see if I see the syntax error. A simple way to make sure I am changing the right file.

Thank you for your comments! I am away for the weekend so can't try this out, but will report back when I do.

Incidentally, do you think it's possibly because I am using set_propagated_delay for the clock (to answer your question this is pre-PnR but I do have buffers on my clock path as you can see, and I have said nothing about wire loads in my constraint file so this is using defaults presumably)? I have a vague recollection that I somewhere read that that can override any other clock settings. Could that be the culprit? I would have thought that set_propagated_clock defined clock behaviour within the circuit, with no problem using set_transition_time to define how the clock (skew) is delivered (from outside) to the design, but perhaps this is not correct.

 

[EDA_beginner0]

Actually in PT, if you use "set_propagated_clock [get_clocks CLK]", then "set_clock_transition 2 [get_clocks CLK]" will be ignored . The transition of clock pin will the be the value that is caculated . If you want to check the transition value in pin , you can add "-transition_time" option after report_timing

 

[EE18]

Actually in PT, if you use "set_propagated_clock [get_clocks CLK]", then "set_clock_transition 2 [get_clocks CLK]" will be ignored . The transition of clock pin will the be the value that is caculated . If you want to check the transition value in pin , you can add "-transition_time" option after report_timing

Thank you! But one further question remains: surely there must be some way to set the clock transition rate which is seen at the external CLK port? That's what I'm trying to do here. I get that set_propagated_clock uses the delay calculated values for the clock once it's in the design, but surely I should be able to apply different slews from the outside to the design as a whole?

 

[ThisIsNotSam]

yes, you can do it with sdc commands

 

[EE18]

yes, you can do it with sdc commands

Possible to elaborate on which ones? I can't seem to find the answer in either the DC or PT user guides.

 

[ThisIsNotSam]

Did you try set_input_transition ?

 

[Mehvish99]

Clock transition time should impact your timing analysis in PrimeTime. If you're not seeing an effect, double-check your clock parameters, timing library, and analysis settings.