Asynchronous D flip flop with preset and clear

Status
Not open for further replies.
B

BB11

Member level 4
Joined
Jan 4, 2010
Messages
74
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
india
Activity points
1,828
Hello

Can you please confirm if this is the circuit diagram is correct for Asynchronous Positive edge triggered D flip flop with preset and clear? I am not getting expected results only for 1 condition : when Preset =1, clear=0 -- expected output Q=1 but it shows Q=0.

Can you please advice?

Thanks
 

Attachments

  • async.JPG
    26.5 KB · Views: 181

Hi,
BB11 said:
esults only for 1 condition : when Preset =1, clear=0 -- expected output Q=1 but it shows Q=0.
Click to expand...
Preset = 1: since Preset is LOW active --> Preset is not active
Clear = 0: since Clear is LOW active --> Clear is active

So when Preset is not active, while Clear is active, I expect Q to be 0.

Klaus
 
KlausST said:
Hi,

Preset = 1: since Preset is LOW active --> Preset is not active
Clear = 0: since Clear is LOW active --> Clear is active

So when Preset is not active, while Clear is active, I expect Q to be 0.

Klaus
Click to expand...
Hello

Please check this output
 

Attachments

  • asyn_output.JPG
    268.4 KB · Views: 162

Hi,

I´ve had a quick view. I found nothing unusual with the FF behaviour.

..But with your test setup:
* CLK is slower than other signals. Does this make sense?

I assume your test setup is not very useful. --> make CLK the fastest signal or setup for special cases

Klaus
 
Reactions: BB11

    B

    BB11

    Points: 2
    Helpful Answer Positive Rating


Thank you.. I will update the clock
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…