Asynchronous D flip flop with preset and clear

[BB11]

Hello

Can you please confirm if this is the circuit diagram is correct for Asynchronous Positive edge triggered D flip flop with preset and clear? I am not getting expected results only for 1 condition : when Preset =1, clear=0 -- expected output Q=1 but it shows Q=0.

Can you please advice?

Thanks

 

[KlausST]

Hi,

Flip-flop (electronics) - Wikipedia

en.m.wikipedia.org

Klaus

 

[BB11]

Hi,

Flip-flop (electronics) - Wikipedia

en.m.wikipedia.org

Klaus

Thank you.
The circuit design is still the same, and I wonder why I am not getting right results when preset is = "0"

 

[KlausST]

Hi,

esults only for 1 condition : when Preset =1, clear=0 -- expected output Q=1 but it shows Q=0.

Preset = 1: since Preset is LOW active --> Preset is not active
Clear = 0: since Clear is LOW active --> Clear is active

So when Preset is not active, while Clear is active, I expect Q to be 0.

Klaus

 

[BB11]

Hi,

Preset = 1: since Preset is LOW active --> Preset is not active
Clear = 0: since Clear is LOW active --> Clear is active

So when Preset is not active, while Clear is active, I expect Q to be 0.

Klaus

Hello

Please check this output

 

[KlausST]

Hi,

I´ve had a quick view. I found nothing unusual with the FF behaviour.

..But with your test setup:
* CLK is slower than other signals. Does this make sense?

I assume your test setup is not very useful. --> make CLK the fastest signal or setup for special cases

Klaus

 

[BB11]

Hi,

I´ve had a quick view. I found nothing unusual with the FF behaviour.

..But with your test setup:
* CLK is slower than other signals. Does this make sense?

I assume your test setup is not very useful. --> make CLK the fastest signal or setup for special cases

Klaus

Thank you.. I will update the clock