A
ahmadagha23
Guest
Hi
I am simulating my vhdl codes by activhdl6.3. In one of the component I have a clock signal arived from input port. When I assigned it to
an inner clock signal without any delay (clk<=inclk
it works but when I assigned it to inner clock with delay (clk<=inclk after 30 ns
the
inner clock (clk) fixed to its initial value. Do you know the reason?
How can I simulate the deskewing by CLKDLL component?
Regards
I am simulating my vhdl codes by activhdl6.3. In one of the component I have a clock signal arived from input port. When I assigned it to
an inner clock signal without any delay (clk<=inclk
inner clock (clk) fixed to its initial value. Do you know the reason?
How can I simulate the deskewing by CLKDLL component?
Regards