assigning a clk with delay. is it possible?

[ahmadagha23]

Hi
I am simulating my vhdl codes by activhdl6.3. In one of the component I have a clock signal arived from input port. When I assigned it to

an inner clock signal without any delay (clk<=inclk it works but when I assigned it to inner clock with delay (clk<=inclk after 30 ns the

inner clock (clk) fixed to its initial value. Do you know the reason?
How can I simulate the deskewing by CLKDLL component?
Regards

 

[goshka]

I have similar problem with active hdl.

I clear all compiled project lib data manualy (view-> lib-manager).

Recompile project.

Problem is removed.

 

[rakko]

This sounds like a setup or hold problem. As a rule of thumb the data has to arrive at the 1st flip-flop before the clock by at least a setup time of the flip-flop. If you manually push the clock out too close to the edge or even past the current data, it will fail. Have you done a timing analysis on this path to see what spice or primetime thinks is happening ?

I would write a behavioral model of your DLL and use it in your simulation. There are lots of documents on how to do this on the web. DLLs are more complicated than just pushing the clock forward. For one they are typically a dynamic circuits with the ability to adjust the clock in both direction with respect to some input stream.....