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Ask a question about clock tree

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liujingshu

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Hi,guy
I want to ask a question about clock tree. If clock2 is divide by clock1 which is the port clock, and how to clock tree synthesis about the clock2??
 

linuxluo

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hi,
in current flow, normally CTGen will synthesize clock2 tree as clock1, but if you specify that clock1 is sync with clock2 in your clock definition file, they will be balanced .
 

jcchan

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if clock2 is generated form flip flop then clock2 tree is differ from clock1 and you must leaf or exclude in flip flop by your application.
 

visualart

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In new version tool, CSTgen can deal the devide clock, gate clock from the smae original clock cource as a clock.
 

jackson_peng

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for a generated clk2, do CTS on the clk2 first, and then set the clk2 root as an sync pin in clk1 CTS.

for a gated clk2, just do CTS on clk1 and no further operation is needed
 

woodyplum

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combine with the design code, you can solve it in the design phase with out the balance of these two CTS
 

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