Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

ASIC Design, file extention flow!

Status
Not open for further replies.

mami_hacky

Full Member level 6
Joined
Mar 28, 2002
Messages
337
Helped
18
Reputation
36
Reaction score
11
Trophy points
1,298
Location
Some where
Activity points
3,428
Who can give me a list of file extentions used in synopsys ASIC design flow?

for example, for xilinx FPGAs I say this:
*.v -> Synthesis -> *.edf
then *.edf and *.edn and *.ncf and *.ucf -> ngdbuild -> *.ngd
*.ngd -> map -> *.ncd
*.ncd and *.pcf -> par -> *.ncd

I want a same diagram for synosys ASIC design flow. Who can help?
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top