a1129m
Newbie level 2
Hi All,
In ASIC design what are the best practice/industry standard for back-pressure (stall) mechanism.
Example -
Consider ASIC datapath with N-pipeline stages, where last stage is a FIFO which writes data into a shared memory (i.e. there are other independent blocks accessing the memory as well, and write-access to memory is not guaranteed).
Scenario 1) First (N-1) stages are all comprised of "combo logic" followed by registers to store outputs of each stage. There is no "feedback" from registers (e.g. no accumulators).
If last stage FIFO ("output FIFO") gets full and is unable to write anymore into the shared memory ....... we would need to "freeze" all previous (N-1) stages immediately.
=> How should this be implemented ? A "output FIFO full" signal that acts as clk-gating signal to all previous (N-1) stages ? If N is large, this might be a high-fanout net and might cause synthesis setup-violations. Is there any alternative solution ? How is this done in industry ?
Scenario 2) If somewhere in the middle (say N/2 stage) is an accumulator pipeline stage, which accumulates 'M' terms before providing valid output to next stage. All remaining (N-1) stages are same as B]Scenario 1[/B].
If last stage FIFO ("output FIFO") gets full and is unable to write anymore into the shared memory for -
* Less or equal to M cycles
* Greater M cycles
=> How do we implement stall/back-pressure ? It seems that we can (and should) allow pipe-line stages before accumulator to continue working upto additional M-cycles. What about stages after accumulator. How would stall/back-pressure mechanism be implemented ?
I would be grateful for any in-depth suggestion (also I would like to know if there is any recommended book regarding this matter).
Thanks,
a1129m
In ASIC design what are the best practice/industry standard for back-pressure (stall) mechanism.
Example -
Consider ASIC datapath with N-pipeline stages, where last stage is a FIFO which writes data into a shared memory (i.e. there are other independent blocks accessing the memory as well, and write-access to memory is not guaranteed).
Scenario 1) First (N-1) stages are all comprised of "combo logic" followed by registers to store outputs of each stage. There is no "feedback" from registers (e.g. no accumulators).
If last stage FIFO ("output FIFO") gets full and is unable to write anymore into the shared memory ....... we would need to "freeze" all previous (N-1) stages immediately.
=> How should this be implemented ? A "output FIFO full" signal that acts as clk-gating signal to all previous (N-1) stages ? If N is large, this might be a high-fanout net and might cause synthesis setup-violations. Is there any alternative solution ? How is this done in industry ?
Scenario 2) If somewhere in the middle (say N/2 stage) is an accumulator pipeline stage, which accumulates 'M' terms before providing valid output to next stage. All remaining (N-1) stages are same as B]Scenario 1[/B].
If last stage FIFO ("output FIFO") gets full and is unable to write anymore into the shared memory for -
* Less or equal to M cycles
* Greater M cycles
=> How do we implement stall/back-pressure ? It seems that we can (and should) allow pipe-line stages before accumulator to continue working upto additional M-cycles. What about stages after accumulator. How would stall/back-pressure mechanism be implemented ?
I would be grateful for any in-depth suggestion (also I would like to know if there is any recommended book regarding this matter).
Thanks,
a1129m