@vyella1 Thanks for replying.
Let me clarify your suggestion -
Assumption:
"Scenario 1" with N=7 (7th stage being output-FIFO).
Proposal:
* Create (fifo_ptr == (FIFO_DEPTH-6-1)) signal and use this to stall Stage-1 (and let Stage-2 to 6 continue operation)
* <Unconfirmed> Most likely you are also proposing to stall subsequent stages with unique signals e.g. (fifo_ptr == (FIFO_DEPTH-6-2)) signal to stall Stage-2 etc
Issue:
* This solution is much more complicated than simply stalling ALL stages (i.e. 1 to 6) when (fifo_ptr == (FIFO_DEPTH-1)).
* The proposed solution creates "bubbles" that we will need to track, when finally output-FIFO offloads data to shared memory i.e. when operation resumes (because data coming in to various stages is no longer valid).
* From overall HW-architecture point of view, the proposed solution doesn't provides any advantages ........since these "bubbles" will negate any possible benefit we could have achieved by allowing other stages to function normally (i.e. stalling only Stage-1, not Stage-2,3,4,5,6 when "(fifo_ptr == (FIFO_DEPTH-6-1))" ).
I'm facing a problem which is lot more complicated than above two scenarios ...... I'm hoping for simple/elegant solution that I can scale up to arbitrary complexity. Let me know your thoughts.
a1129m