Are systemverilog assertions synthesizable by Synopsys Design Compiler

[tariq786]

Are systemverilog assertions synthesizable by Synthesis tools

Are systemverilog assertions synthesizable by synthesis tools like Synopsys Design Compiler or other synthesis tool?

How about Xilinx ISE suite?

Please explain.

Thanks

 

[hdlcohen]

Re: Are systemverilog assertions synthesizable by Synthesis tools

Are systemverilog assertions synthesizable by synthesis tools like Synopsys Design Compiler or other synthesis tool?

How about Xilinx ISE suite?

Please explain.

Thanks

NO. assertions are used for verification. Synthesis if for conversion of RTL into gates.
Conversion from SVA to gates is not supported.
Ben Cohen
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Ben Cohen (831) 345-1759
https://www.systemverilog.us/ ben@systemverilog.us
* SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN 878-0-9705394-8-7
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
* Component Design by Example, 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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[tariq786]

Ben i am a big fan of yours.

Could you tell which assertions are synthesizable?

Thanks again

 

[hdlcohen]

<Could you tell which assertions are synthesizable?>
None.
There is such a thing as "Assertion Synthesis", but that takes rtl and coverts it into assertions.
See
**broken link removed**
Ben Cohen
SystemVerilog.us

 

[er.akhilkumar]

The assertions written by using ASSERT in VHDL are syntheisizable. To block this synthesizability we use synthesis pragmas for example for synopsis we use "--synthesis translate-off" pragma.

Although assertions can't be translated to a circuit yet it is harmfull if synthesis tool mistakes the assertion syntax. I think System verilog assertions are also synthesized by the Synopsis and for blocking this we should also have some pragmas.

 

[hdlcohen]

The assertions written by using ASSERT in VHDL are syntheisizable. To block this synthesizability we use synthesis pragmas for example for synopsis we use "--synthesis translate-off" pragma.

Although assertions can't be translated to a circuit yet it is harmfull if synthesis tool mistakes the assertion syntax. I think System verilog assertions are also synthesized by the Synopsis and for blocking this we should also have some pragmas.

SVA concurrent are not synthesizable. They are used only for verification. In fact, it is generally preferred that SVA assertions be put in a module bound to a DUT so as isolate the verification code from RTL,and to avoid resynthesis of good RTL code because of a timestamp change due to SVA verification code if that code were directly embedded into the DUT.
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Ben Cohen, Design and verification expert (310) 997-2187
https://www.systemverilog.us/ ben@systemverilog.us
* SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN 878-0-9705394-8-7
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
* Component Design by Example, 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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