univer_solar
Member level 4
Hi all,
I use PKS tools of Cadence to synthesize project have top module. It's OK and generate netlist.v. But when I use SoC Encounter to read this netlist file it doesn't appear the die size as general. I can't define floorplaning for it. It's give an error message. Pls help me.
Thanks
I use PKS tools of Cadence to synthesize project have top module. It's OK and generate netlist.v. But when I use SoC Encounter to read this netlist file it doesn't appear the die size as general. I can't define floorplaning for it. It's give an error message. Pls help me.
Thanks