When you synthesized your netlist, did u target the design to an ASIC technology library such as TSMC 90nm or 180nm? Could you also post the exact error message you receive from SoC?
Generally, after synthesis using BuildGates or PKS, we write the new netlist as a Verilog file. This netlist is imported into SoC by specifying the std cell libraries, timing libraries, and other info. When the import is done, the SoC window will show a block , ie, the core area alone along with the design as a set of blocks (this depends on your design hierarchy). . Now we define the core size, the core to IO distance, etc.
I suggest you go through the tutorial at this website:
**broken link removed**