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With SETSOA and CHECKSOA you can verify that no device in your design is stressed by overvoltage or overcurrent, among others.
Before all, use the RTFM procedure. (Read The Fucking Manual. It is not so hard to understand how it works.
Example to verify if the Vgs voltage of a transistor is greater than abs(5.5V)
.setsoa label="Vgs your_MOS_model limit reached" M your_MOS_model Vgs(*)=(-5.5,5.5)
Example to verify if current denssity on a given resistor material is greater than abs(0.09mA/um). In this example the resistor, called r1, is defined inside a SUBCK. Put the SETSOA statement inside the SUBCKT definition.
.setsoa label="Current density through your_RESISTOR_model resistor exceeds limit (0.09mA/um)" E i(r1)/(1e6*w)=(-0.09m,0.09m)
Humungus,
Thanks for your explanation.
HSPICE doesn't have this feature. It seems your examples also can use the calculator to get the answer. What are the advantages for this Eldo's special feature?
does 0Eldo have more advantage over hspice,whta is the special function purpose in simulation and why not use hspice?
Added after 6 minutes:
I have checked it in the webserach,the eldo simulation tools can shorten the simulation period and many companies such as hair has taken it in its analog simulation,the tool contains many algorhithems in it but I have not met anyone in my lab used it.and does anyone introduce the popularity of it in your surrounding
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