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any one can share DLL and IO of SSTL_2 's data sheet?

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kinysh

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I want to have some detail info about DLL and IO of SSTL_2. for DDR
especially the timing, such as the DLL accuracy, and SSTL_2 IO pad delay.

Bests
kinysh
 

cmoscircuit

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PSSTL2 TPD973G_SSTL2

--------------------------------------------------------------------------------

SSTL_2 IO BUFFER
Truth Table
INPUT OUTPUT
PWD OEN I PAD C
0 1 X 0 0
0 1 X 1 1
0 1 X Z X
0 0 0 0 0
0 0 1 1 1
1 1 X 0 0
1 1 X 1 0
1 1 X Z 0
1 0 0 0 0
1 0 1 1 0


Cell Information
Cell Name No. Pad Req. Power (uW/MHz)
PSSTL21X 1 23.66
PSSTL22X 1 45.45

Pin Capacitance (pF)
Cell Name C I OEN PAD PWD
PSSTL21X 0.032 0.036 0.022 2.238 0.016
PSSTL22X 0.032 0.036 0.022 3.312 0.016


--------------------------------------------------------------------------------
Propagation Delays (ns)
Cell Name Delay Sample Loads (pF) Performance
Equation
Path Out Dir 10 30 50 125
PSSTL21X OEN-> PAD EnRise 1.90 2.36 2.82 4.55 1.674+0.023 Cld
EnFall 2.00 2.48 2.96 4.76 1.765+0.024 Cld
tpLZ 1.75 1.75 1.75 1.75 1.746
tpHZ 1.48 1.48 1.48 1.48 1.480
I-> PAD Rise 1.72 2.16 2.60 4.25 1.500+0.022 Cld
Fall 1.85 2.31 2.77 4.50 1.623+0.023 Cld
PSSTL22X OEN-> PAD EnRise 1.78 2.04 2.30 3.27 1.645+0.013 Cld
EnFall 1.86 2.12 2.38 3.35 1.729+0.013 Cld
tpLZ 1.86 1.86 1.86 1.86 1.855
tpHZ 1.56 1.56 1.56 1.56 1.557
I-> PAD Rise 1.65 1.91 2.17 3.14 1.519+0.013 Cld
Fall 1.77 2.03 2.29 3.26 1.636+0.013 Cld
Propagation Delays (ns)
Cell Name Delay Standard Loads Performance
Equation
Path Out Dir 2 4 8 16
PSSTL21X PAD-> C Rise 1.04 1.05 1.06 1.09 1.038+0.298 Cld
Fall 1.05 1.05 1.07 1.10 1.038+0.395 Cld
PSSTL22X PAD-> C Rise 1.04 1.05 1.06 1.09 1.038+0.298 Cld
Fall 1.05 1.05 1.07 1.10 1.038+0.395 Cld

VDDIO = 2.3V, VDDCORE = 1.62V, TEMP = 125 degree C, PROCESS = Slow-Slow
standard load = 0.01pf, input slew time = 0.06ns (measured from 10% to 90%)
 

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