Analog Layout - Matching analysis

[RodrigoSP]

Hi everyone,

I want to collect some inputs and maybe start a discussion here on what are your best practices when handling complex matching structures.

Often I see people struggling with complex matched MOS arrays on whether to simplify the pattern to have a cleaner routing and therefore less parasitics; or when to keep the pattern more distributed to improve the matching.
Since the parasitics can be easily extracted and backannotated, but the mismatch due to pattern and devices location not, how do you normally handle these two competing aspects?

 

[Dominik Przyborowski]

Bsim4 introduces LOD and WPE, so placement is taken into account. The latest tools start to adding thermal effects as well.

What we have to guess is wafer gradients in doping or oxide thickness and this is arbitrarily decision.

 

[timof]

It's not so much about "less" parasitics, but about "matched" (or "weighted") parasitics.
Mismatch in parasitics can destroy matching of your devices or nets.

 

[RodrigoSP]

It's not so much about "less" parasitics, but about "matched" (or "weighted") parasitics.
Mismatch in parasitics can destroy matching of your devices or nets.

Very good point. Thanks for bringing it up

 

[timof]

When matching requirements are stringent, like 1%, or 0.1%, or 0.01% - verifying parasitics matching is not an easy thing to do.
Even extraction tool accuracy comes into question, at this accuracy level (you can use a field solver option, to guarantee accuracy).
Next, C distribution over R network comes into question, and extraction tools can do a very poor job here.