umagne
Newbie level 6
cadence layout automatic placing and routing
Hi everyone,
I'm new to (analog) layout and I'm trying to start my new activity with a standard voltage reference. I use a 0.18um technology with the Cadence environment (in particular the section Custom IC Design).
Starting from the schematic entry in the virtuoso environment, once chosen the aspect ratios of my transistors, I convert my schematic in the specific layout.
At this point, it seems to me, Virtuoso offers two optional procedures.
Design the transistors starting from the layers provided by the technologies (Manual flow) or generating the instances from the schematic source and routing them with the appropriate layer (Automatic flow).
I'd like to follow the Automatic flow and I'd be pleased if someone could suggest to me the right way of design the layout of an analog circuit.
With the Automatic flow what can I change in the transistors created by the system? Can I interdigitate two transistors or they remain separate instances.
The guard rings should cover the entire voltage reference or the single transistors?
Thanks.
Hi everyone,
I'm new to (analog) layout and I'm trying to start my new activity with a standard voltage reference. I use a 0.18um technology with the Cadence environment (in particular the section Custom IC Design).
Starting from the schematic entry in the virtuoso environment, once chosen the aspect ratios of my transistors, I convert my schematic in the specific layout.
At this point, it seems to me, Virtuoso offers two optional procedures.
Design the transistors starting from the layers provided by the technologies (Manual flow) or generating the instances from the schematic source and routing them with the appropriate layer (Automatic flow).
I'd like to follow the Automatic flow and I'd be pleased if someone could suggest to me the right way of design the layout of an analog circuit.
With the Automatic flow what can I change in the transistors created by the system? Can I interdigitate two transistors or they remain separate instances.
The guard rings should cover the entire voltage reference or the single transistors?
Thanks.