Analog layout - Cadence

[umagne]

cadence layout automatic placing and routing

Hi everyone,
I'm new to (analog) layout and I'm trying to start my new activity with a standard voltage reference. I use a 0.18um technology with the Cadence environment (in particular the section Custom IC Design).
Starting from the schematic entry in the virtuoso environment, once chosen the aspect ratios of my transistors, I convert my schematic in the specific layout.

At this point, it seems to me, Virtuoso offers two optional procedures.
Design the transistors starting from the layers provided by the technologies (Manual flow) or generating the instances from the schematic source and routing them with the appropriate layer (Automatic flow).

I'd like to follow the Automatic flow and I'd be pleased if someone could suggest to me the right way of design the layout of an analog circuit.

With the Automatic flow what can I change in the transistors created by the system? Can I interdigitate two transistors or they remain separate instances.

The guard rings should cover the entire voltage reference or the single transistors?

Thanks.

 

[oermens]

analog layout with cadence tools

Personally I recommend everyone should do their first layout by hand, not just for understanding the physical design aspect but also to appreciate the tools and their capabilities.

By "Automatic Flow" I think you mean Schematic-Driven Layout, which is achieved using Virtuoso XL, provided your PDK comes with scalable parameterized cells (PCells). Transistors can be merged but I think it depends on the capability of your PCells. Refer to $CDSHOME/doc/vxlhelp/vxlhelp.pdf regarding this tool. Place and route tools is not too common for analog layout (I think), but you can use Virtuoso Chip Assembly Router to perform this task. I have limited experience with this tool, but I found that unless you spend lots of time setting up the rules for the router, it doesn't do a good job.

 

[umagne]

anlog layout interdigitate design

Personally I recommend everyone should do their first layout by hand, not just for understanding the physical design aspect but also to appreciate the tools and their capabilities.

By "Automatic Flow" I think you mean Schematic-Driven Layout, which is achieved using Virtuoso XL, provided your PDK comes with scalable parameterized cells (PCells). Transistors can be merged but I think it depends on the capability of your PCells. Refer to $CDSHOME/doc/vxlhelp/vxlhelp.pdf regarding this tool. Place and route tools is not too common for analog layout (I think), but you can use Virtuoso Chip Assembly Router to perform this task. I have limited experience with this tool, but I found that unless you spend lots of time setting up the rules for the router, it doesn't do a good job.

I don't think I'm using the Schematic-Driven Layout, I use Virtuoso XL: given a schematic Entry, I create the layout from the command Generate From Source. The system places the transistors separately, I'm asking if there is an option to make interdigitate transistors. The file you suggest "vxlhelp.pdf" isn't so clear for this purpose.
Could anyone suggest me a way to solve this problem?
Thanks.

 

[oermens]

schematic driven layout cadence

Schematic-driven layout = VirtuosoXL. move the two transistors immediatly side by side. if your pcell supports mosfet abutment they will merge

 

[umagne]

analog auto place and route

How can I see if my Pcell (transistor) supports abutement or how can I activate this feature on the pcell of my design kit?
Thanks

 

[oermens]

analog layout cadence

Check the documentation for your PDK's PCells or contact your foundry to see if mosfet abutment is supported. I don't think its something you can set on your own.