Analog IC Layout design in Cadence Virtuoso

[Karan Singh]

Hello All
I am new to using Cadence Virtuoso tool for the purpose of analog design. I have to build a gilbert cell multiplier using the NCSU FreePDK 45nm technology. I have Cadence Virtuoso suite with Mentor Graphics Calibre for DRC/LVS.

For people who have used the NCSU Analog Lib for analog design, could you tell me how I can model components such as vccs, cap etc for simulation in schematic ? Also how I can build physical layouts of the components ?

I have read tutorials on analog inverter design but they don't demonstrate how they make layouts.

Please help.

 

[dick_freebird]

analogLib has all that stuff. One of the standard libraries that
comes with the setup.

 

[diaz080]

check analogLib library..

Also how I can build physical layouts of the components ?

open the layout window in cadence LAUNCH-> LAYOUT XL ..place all the required components and bulid the circuit..
Go through this tutorial before you start doing layout :wink:

 

[Karan Singh]

Hello Kannan
Thank you for your response.
I know the digital design bit pretty well. I was wondering how different it is in Analog.

Would you be having a schematic+layout tutorial on a analog circuit like OPAMP/ Summing Amplifier ?

- - - Updated - - -

analogLib has all that stuff. One of the standard libraries that
comes with the setup.

Hello dick_freebird.
Thank you for your response.
Suppose I have a PWL input in the INVERTER schematic, is there a need to model that in layout ?
If yes how do you model such components (There are many such in the analog lib).

Also for the purpose of simulation using ADE L, is it possible to use the Spectre simulator with the existing hSpice models ? If so, how does one do that. Are there any additional softwares needed to be installed ?

 

[diaz080]

friend,.you need to brush up your concept about layout design..first start from basics..build layout of an inverter circuit..make it lvs and drc clean..only when u solve the drc and lvs error ..u will get the clear picture..then think about complex circuit..ok..:lol:

 

[Karan Singh]

Friend,
I have worked at ST Micro before and designed standard cells there, I know my way around Cadence Virtuoso and DRC & LVS.

I am doing this new project in college which involves analog design and I don't know much about this. So i go back to the question I asked earlier.

 

[dick_freebird]

The analogLib primitives do not exist in layout, they are more
for testbench externalities (anything laid out, will properly
come from the foundry PDK libraries / techfile). If you try
to LVS a hierarchy that has them present, the best case
is benign (resistors act as shorts, capacitors as opens,
etc.) but more likely you will get some mismatches because
these things have no valid layout aspect.

You want your physical design cell to be complete and
without anything that isn't "real" (other than, perhaps,
some global-tie and noconn instances). If you want to
test it in simulation, place it -in- a testbench schematic
rather than trying to pepper a layout-destined schematic
with things that can't be laid out.

 

[Karan Singh]

So is there a different tool for post layout simulation ? Used cosmos cope earlier.

Also dick_freebird can you point to the direction where I can find more material on Analog design using Virtuoso ?