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Altium Routing: through vias being split into two blind vias. Additional question about blind via costs / benifits

Hawaslsh

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Hello all,

I am using Altium designer and I am routing a 4 layer board for the first time. I have run into an issue using vias during interactive routing. I will be routing a line on the bottom side (layer 4) and want to move to the topside (layer 1) using a via. During interactive routing I will hold down shift and control and scroll the center mouse wheel to change layers. When i intended to put a through via, Altium will instead place two blind vias, one from layer 4 to layer 2, and a second from layer 2 to layer 1. Is this normal? Should i have changed something in my design rules?

Bonus question: I am routing some RF lines on the top layer. The PCB fab house tells me the upper pre-preg layer will be 110um thick and give me an er = 4.29, so I could use microstrip or co-planar waveguide and stay within the cheapest fabrication tolerance, 6mil lines and spaces to create 50 ohm lines. Most RF eval boards I see use co-planar waveguide, but on a 4 layer board this would require blind bias (from the top layer to an inner ground plane) in order to create my RF shielding and ensure the top layer ground plane and inner ground plane are connected. I hear using blind vias increase my price. In general is that price increase proportional to the number of blind vias, or somewhat a fixed added cost? I could microstrip lines to avoid using A LOT of blind vias, but most of the analog chips will need blind vias regardless to be grounded to the inner layer. Is there a larger benefit to using CPW over microstrip that would make the added costs worth it?

Happy to provide more context,
Thanks in advance,
Sami
 

FvM

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You apparently missed to define all-through vias as possible (in case of doubt default) via option for your board. In addition, I absolutely don't understand why vias of a coplanar ground fence should not go through all layers. May be you forgot to mention specific design details of your board.
Generally speaking, blind and burried vias will be only used to serve a specific purpose that can't be achieved otherwise. Unless the via count is very high, cost increase is per via type used in a design. E.g. +xx % for using 1-2 blind vias. 4-2 blind vias would require additional sequential processing and involve a large cost increase, if feasible at all. All non-standard via options should be agreed with the manufacturer before starting the design.
 

Hawaslsh

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I absolutely don't understand why vias of a coplanar ground fence should not go through all layers.
The via fence wouldn’t be through vias, they would be blind vias from the top layer to the internal ground plane below. That lead to my other question of the comparison between using microstrip vs CPW. Microstrip would greatly lower the number of blind vias (probably lowering cost) but I don’t usually see RF eval boards using microstrip.
 

FvM

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The via fence wouldn’t be through vias, they would be blind vias from the top layer to the internal ground plane below.
Why particularly?
--- Updated ---

That lead to my other question of the comparison between using microstrip vs CPW.
It's actually CPW with ground rather than plain CPW. The difference to microstrip is small or greater, depending on the actual geometry. Reasons to use CPW with ground can be smaller width or reduced crosstalk to other signals traces. Only 0.11 mm substrate height doesn't suggest CPW as preferred technology. What's the substrate material?
 
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Hawaslsh

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Why particularly?
I don't do much PCB work, i guessed that's what's normally done. But looking at some of the RF eval boards we have, both the via fences and ground vias for a chip's exposed pads are through holes. I suppose I thought having what amounts to an added 1.2mm open stub would affect the results. But if Ti and Analog Devices uses through vias on parts up to 40 GHz it will work for my much lower frequency design.
What's the substrate material?
Cheap FR4. I am not going high in frequency, up to 4 GHz. I use to use a 0.8mm thick 2 layer board with some GCPW lines using the same fab house and the loss wasn't too bad at 4 GHz, ~0.01dB/mm. There are very short traces that carry the RF signal before it gets down converted.

I am transferring the original 2 layer design to 4 layers to more easily route SPI, GPIO, and power lines. I used GCPW prior since the substrate was rather thick. But as you suggest, with a substrate thickness of 0.11mm microstrip is viable.

Thanks again for your time and help!
 

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