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This circuit consists of two transmission gates.The top transmission gate is present so that the previous data can be read out in the absence of a positive clock i.e.(when Φ=0) .Consider if no inverters were to be present,whenever the transmission gate is OFF,its output is Z(High Impedence).This causes the previous state value to be read as Z(High Impedence).In order to avoid this , two inverters are present. Anyways a minimum of two inverters are required.The inverter is present before the transmission gate so as to get both the outputs Q and Q'.Hope this helps.
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