ADS - layout - generating schematic from layout

[jdstavares]

I designed a rectifier circuit, and verified every mlins and components to not be overlaped. However when i generate the schematic from layout one of the cpads gets offset being misplaced over the layout. How can I put it the right place?
I already forced the nets to be exactly as the schematic.

Also, in some components I noticed that a yellow triangle - like a warning sign - appears. I click on it and it does not explain the reason for it appearance. I thought it was due to some overlap, but at the beggining, when testing to place each component at a time from the schematic to the layout, that also happened, so not really sure about the reason why.

And about the clearance, is there a minimum value? I saw some papers, that claimed that the 3w rule is not necessary, so that I can just put some value, but did not fully understand it...

Can anyone help me?
Thank you!

 

[RealAEL]

Would need more information to comment on your first and third questions but I can tell you about the yellow icons. These are not warnings but "stretch handles". They will appear on straight transmission line components in layout view when they are selected individually. You can then place your cursor over the icon, hold the mouse button down and graphically pull the transmission line to the desired length. The length ("L" parameter) will be updated automatically to the new dimension.

 

[jdstavares]

Would need more information to comment on your first and third questions but I can tell you about the yellow icons. These are not warnings but "stretch handles". They will appear on straight transmission line components in layout view when they are selected individually. You can then place your cursor over the icon, hold the mouse button down and graphically pull the transmission line to the desired length. The length ("L" parameter) will be updated automatically to the new dimension.

@RealAEL thank you the answer.

Well to explain in more detail the first question I have here both the schematic and the layout. As you see, in the schematic the sum of both the c_pads and the mlins lengths performs always the same result, in order to generate a layout equal to the schematic. But when you see the layout you verify a shift in the stubs and mlins. Besides, you can see some overlap, which should, not happen, right? I think that overlap is due to the mtees, but not sure.

And to reffer to the third question, when inserting the ground, I had to put a clearance, and I put 0.5 mm, but how do I know it's the best value? In the papers, they claim that you can define clearance as 0.1 mm and forget the 3w rule. So it doesn't matter that much?

 

[volker@muehlhaus]

But when you see the layout you verify a shift in the stubs and mlins. Besides, you can see some overlap, which should, not happen, right?

It seems that there is a conflict of dimensions, so that your closed path doesn't end where you expect. For example, MTEE always have finite size ... each MTEE will add some length on thru direction that depends on width W3. These small effects can add up, so it requires a lot of calculation to make the auto-generated layout fit exactly.

You can adjust dimensions in layout (to make layout work) and then back-annotate changes in length to schematic.

In the papers, they claim that you can define clearance as 0.1 mm and forget the 3w rule.

That makes no sense. Required clearence does depend on line width and substrate width. In your case, clearance is much too small. I recommend to use rule 3*max(width, substrate thickness), or leave out top ground completely for microstrip circuits.

 

[RealAEL]

As Volker explained you have many "loops" in this design and there does seem to be many offsets in the dimension around each loop. There could be many contributors to this situation but getting using incorrect size adjustments for the TEEs and lumped component pads are likely causes of unexpected offsets. These dimension offsets need to be fixed to resolve the issues with this design.

The primary obstacle to fixing this is that ADS, when generating such a layout, simply places the component one at a time connecting the next in sequence to any that is already placed. You have no control over this order, unless you place them manually one at a time (using Layout > Place Component From Schem To Layout) which would be slow. When working on a circuit like this I would remove one connecting wire from each and every loop. This forces the "break" to be in a predetermined position is each loop and from that it would be more obvious what was both the horizontal and vertical offset that needed to be corrected. Making the necessary corrections one loop at a time would let you find the correct solution for the entire design and once each loop connects correctly the wires can be reinstated.

 

[jdstavares]

Thank you @RealAEL and @volker@muehlhaus

I'm also having this error:

But the thing is, I checked on the design report, and " There are no unconnected pins. There are no nodal mismatches. There are no wires in layout. There are no nets in the layout whose objects do not touch. There are no net overlap zones in the layout. Manufacturing grid is disabled in the layout. There are no pcell evaluation errors in the layout hierarchy. There are no parameter value mismatches. Overlaid items: Overlapping wires/traces not on the same net: None"

So not sure what is really happening here...

 

[RealAEL]

For EM simulation the pins (ports) need to be on the edge of the metal shapes and cannot be inside the profile of the traces.

The pin on the lower right seems to be fine. You are able to "drift" this to the outer edge, away from the point pin, as required because the pads for the R_Pad/C_Pad components are defined as area pins so the connecting pin can be located anywhere around the edge or inside the profile of the pad.

The pin on the left is not allowed to be in the middle of the conductor but this cannot be moved and remain connected as these shapes are not area pins. You would need to adjust your circuit perhaps by using a CROSS, instead of the TEE, to have a pin on that edge for connecting the port connection.

Be aware though that placing the port connection on a trace edge like this utilizes the entire straight edge segment of all the connected components as the feed location. So, on the left the entire outer edge of the TEE/MLIN/MCORN and on the right the MLIN/MCORN would be the feed location. If you use the CROSS method mentioned above, it would be possible to add a very short MLIN (you decide the width) to set this edge.

 

[jdstavares]

For EM simulation the pins (ports) need to be on the edge of the metal shapes and cannot be inside the profile of the traces.

The pin on the lower right seems to be fine. You are able to "drift" this to the outer edge, away from the point pin, as required because the pads for the R_Pad/C_Pad components are defined as area pins so the connecting pin can be located anywhere around the edge or inside the profile of the pad.

The pin on the left is not allowed to be in the middle of the conductor but this cannot be moved and remain connected as these shapes are not area pins. You would need to adjust your circuit perhaps by using a CROSS, instead of the TEE, to have a pin on that edge for connecting the port connection.

Be aware though that placing the port connection on a trace edge like this utilizes the entire straight edge segment of all the connected components as the feed location. So, on the left the entire outer edge of the TEE/MLIN/MCORN and on the right the MLIN/MCORN would be the feed location. If you use the CROSS method mentioned above, it would be possible to add a very short MLIN (you decide the width) to set this edge.

View attachment 179569

I did as you said, for the P1 I used a cross and a short mlin, however the error still goes on....
"ERROR : At least one port pin or bondwire end is not fully connected to a conductive part of the design (see the layout processing report for details).This setup is invalid for a Momentum simulation."

But when I go to the design report there's nothing that points to that error:

 

[RealAEL]

Try doing something different at the other pin. The fact that you are relying on an area pin and not a point pin may be the issue.

If you use a MTEE instead of that MCORN this would leave an available pin. Not is exactly the same position but it may give you results to get started. You could also again use a short MLIN to limit the feed edge.

 

[jdstavares]

Try doing something different at the other pin. The fact that you are relying on an area pin and not a point pin may be the issue.

If you use a MTEE instead of that MCORN this would leave an available pin. Not is exactly the same position but it may give you results to get started. You could also again use a short MLIN to limit the feed edge.

Yes, I tried to that after the error, but the same happened