ADC Understanding-AD7693

[Bjtpower_magic]

Hi,
One of my project, ex colleague used AD7693 ADC Converter (https://www.analog.com/media/en/technical-documentation/data-sheets/AD7693.pdf)
i am new to ADC and i need few clarifications.
Since it mentioned that it has sampling rate of 500KSPS but i fail to understand how timing diagram.

Please help me in understanding my assumptions.
1) We have TCYC=2uS=500 KHZ
2) We have TSCK=15nS=66 MHZ

So for each cycle of 66MHZ, it will sample 1 bit so in total for 16bits it will take 16*tsck=16*15=240nS?
So for 1 second, i will have 16bits/240nS=66M bits so my question is how is relation of 500KSPS?
Can you please help me understanding relations?

 

[KlausST]

Hi

Still you mix conversion and communication. These are two different things.
First the ADC internally converts the analog signal into a 16 bit digital value.
After that you can use the SPI to transfer the value.

Klaus

 

[danadakk]

The part has two phases, Acquisition to collect the SAR C array of weight values,
and the conversion phase to convert that arrays state of charges into a digital
value. That at max spped timing takes, worst case, .4 uS uS to get the weighted
values and worst case a max of 1.6 uS to convert those values to digital result.

In parallel with Acquisition process, after last Conversion has completed, one
gets the digital result over SPI with its own timing, which if done right as discussed
prior, does not affect the sample rate.

So .4 uS + 1.6 uS (worst case) = 2 uS = 500K 16 bit SPS.

Note from datasheet :

The AD7693 is a 16-bit, successive approximation analog-todigital converter (ADC) that operates from a single power supply,VDD. It contains a low power, high speed, 16-bit sampling ADCwith no missing codes, an internal conversion clock, and aversatile serial interface port. T

The internal clock sets the timing, for Acquisition and Conversion, and if you keep up with the
SPI you will get the 500K SPS.....


Regards, Dana.

Regards, Dana.

 

[Bjtpower_magic]

If you use a 15 nS clock then you get a bit each falling edge SCK, so you would
get the 16 bits in 15 nS X 16 = 240 nS. You have to complete this before the
Acquisition cycle completes indicated by a rising edge CNV signal. The CNV time
is 400 nS for a 2 uS sample rate.




Regards, Dana.

Hi Dana,
How we know internal clock frequency of ADC, i did check entire datasheet but i did not find.
So as far my understanding,
Conversion time=No of Bits x CLK Time (Not SPI).

is is internal conversion clk is similar to Sampling rate which is TCK=200uS? something else and will know by ADI Manufacturers?

 

[KlausST]

Hi,

there is no need to know the internal clock frequency.

All you need to know is: conversion time = tConv = 0.5...1.6us for converting all 16 bits.
Finished. Don´t make it more complicated.

you refer to TCK = 200uS
.. but a PDF search does neither find "TCK" nor "200us"

I don´t know what you are trying to do and what you are trying to achieve. Please tell us.

Klaus

 

[Bjtpower_magic]

Hi KlausT,

My mistake.. Its TCYC=Aquistion time + Conversion Time=2000uS

I cannot conclude, BIT TIME? Which is to be placed inside shift register... Then Need to check How SPI will read it?
SPI CLK Frequency= FSCK= 66MHZ so each Transferring bit time will be 15nS

 

[KlausST]

I cannot conclude, BIT TIME?

Where do you get the phrase "bit time" from? The datasheet? Which section?

Generally "bit time" means "the time for one bit" ... nothing more. It can be used in many different ways, thus we need to know the context.

Klaus

added:


I´m trying to find out where the problem is. Thus I´m trying to verify if I really understand every information you give.

****
"Which is to be placed inside shift register" I don´t understand clearly. Which shift register are you talking about?
When I search the datasheet for "shift register" then I just find information on daisy chaining multiple ADCs. Is this what you need to do?

***

SPI Clock = SCK: (digital interface = communcation. Has nothing to do with conversion..)
Again: you may choose the frequency. 66MHz is the upper limit. It´s on the edge.(I don´t recommedn to go to the very edge)
As you can see in the timing diagram above:
* t_SCK is the time from falling edge to falling edge.
* and on every falling edge the next bit of the 16 bit conversion result is output on SDO. Starting with the MSB bit D15, then D14, then D13, then D12....consecutive...
So if (again: IF!) t_SCL is 15ns ... then it takes 15ns for one bit, 30ns for two bits, 60ns for 4 bits, 120ns for 8 bits and 240ns for all 16 bits.

***
But why not giving your requirements first:
* what´s the application?
* what´s the SPI master? (PLD, microcontroller ...)
* what´s the analog bandwidth you need?
* what sampling rate do you need (and why)
....

Klaus

 

[danadakk]

Hi Dana,
How we know internal clock frequency of ADC, i did check entire datasheet but i did not find.
So as far my understanding,
Conversion time=No of Bits x CLK Time (Not SPI).

is is internal conversion clk is similar to Sampling rate which is TCK=200uS? something else and will know by ADI Manufacturers?

You do not need to know the internal clock frequency. The part is speced to meet a certain
sample rate. When it is done it informs you an answer is ready to be retrieved. You know
the cycle time of the part is variable, but worst case is the sum of worst case Conv time + min
Acq time. Thats the slowest the part will run. Read page 17 discusses the timing sequence and
considerations and mode you should be in.

Regards, Dana.