Monady
Advanced Member level 4
ADC test
Hi dear all friends;
i've designed an 8-bit SAR ADC. all parts of ADC are made real and all component values are reasonable. only thing that i didn't take into consideration, was mismatch between inputs of comparator.
i performed an INL/DNL test and applied a ramp input with very slow slope, it means ADC has 12 conversions for each LSB (12 outputs with exactly same bits in ideal situation).
But i saw that output of Hspice is almost same as to the ideal ADC. it means, INL and DNL both are less than 0.05LSB!
i'm sure one thing is wrong but which part? maybe i should add noise to simulation.
I would be appreciate for any suggestion.
Hi dear all friends;
i've designed an 8-bit SAR ADC. all parts of ADC are made real and all component values are reasonable. only thing that i didn't take into consideration, was mismatch between inputs of comparator.
i performed an INL/DNL test and applied a ramp input with very slow slope, it means ADC has 12 conversions for each LSB (12 outputs with exactly same bits in ideal situation).
But i saw that output of Hspice is almost same as to the ideal ADC. it means, INL and DNL both are less than 0.05LSB!
i'm sure one thing is wrong but which part? maybe i should add noise to simulation.
I would be appreciate for any suggestion.