Details about Cyclone II FPGA PLL are described in the device handbook, sownloadable from Altera. Minimum PLL output frequency of Cyclone II family is however 10 MHz, so PLL isn't an option to generate the said frequencies. You need to use synchronous counters as frequency dividers which implies a certain delay against system clock. The question is at which place you want matching of clock edges and up to which tolerance? If limits are low, you may want to generate a clock with negative delay by PLL and divide it for the 100 kHz and 1 MHz clock.