About Verilog syntax for parantheses

[sun_ray]

Can we use this following in Verilog

y= ( a | ~b) where a and b are inputs and y is an output?

The reason I ask this question because we are using parantheses () here and in Verilog specification file I am not able to find where () is defined. In the list of operator I do not find () is defined. Is it an allowed construct in Veriliog? If, yes please let me know the section in Verilog Specification file where it is defined. Sometimes we use the following:

y = c | ({d, ( a | ~b)}) where a,b,c,d are inputs and y is an output.

Can anybody explain more on () ? Can this () be used to provide priority in evaluation as it is done in mathematics?

 

[poluekt]

Parentheses can be used to change the operator precedence.

 

[sun_ray]

poluekt

The attached table which has been taken from Verilog IEEE Spec does not show that parantheses can be used to change the operator precedence. This table nowhere has listed parantheses.

Regards

 

[dave_59]

That table is old. Please look at table 11-2 the 1800-2009 LRM which lists () as the highest operator precedence.

 

[sun_ray]

dave_59

I think Verilog do not have any 2009 specification as such. There is a system verilog LRM for 2009 and Verilog does not exist any more after 2009, it is sustem verilog now.

 

[dave_59]

sun_ray,

The Verilog LRM has always had the sentence, Parentheses can be used to change the operator precedence, and the example

(A + B) / C // not the same as A + B / C

The parenthesis were just missing from the table.

You are correct to say there is no more stand-alone Verilog standard. The SystemVerilog IEEE 1800-2005 was created as an extension to the Verilog 1364-2005 standard. However, the SystemVerilog 1800-2009 standard merged the two standards together into one. Any updates to what was in the old Verilog standard goes into the new SystemVerilog standard.

Dave Rich
Co-Chair of the SystemVerilog IEEE 1800-2009 Technical Committee

P.S. SystemVerilog is spelled as one word. :|