About Dsign Cmpile timing report

kjtom said:

Dear all,

I met a confused DC timing log.
The slack calculation resault is very confused.

I list it as followed,

****************************************
Report : constraint
-all_violators
-verbose
Design : SPI_CTRL
Version: 2003.06-2
Date : Fri Sep 22 13:52:57 2006
****************************************


Startpoint: MODE_SEL (input port)
Endpoint: ADC_SEL_tmp_reg
(rising edge-triggered flip-flop clocked by DCLK')
Path Group: DCLK
Path Type: min

Des/Clust/Port Wire Load Model Library
------------------------------------------------
SPI_CTRL WL1K comnlsc06v10

Point Incr Path
-----------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 f
MODE_SEL (in) 0.00 0.00 f
U174/Z (OR02D1) 0.30 0.30 f
U98/Z (ORA21D1) 0.50 0.79 f
U172/Z (MX02D2) 0.55 1.34 f
ADC_SEL_tmp_reg/D (DFCRB1) 0.00 1.34 f
data arrival time 1.34

clock DCLK' (rise edge) 250.00 250.00
clock network delay (ideal) 0.00 250.00
ADC_SEL_tmp_reg/CP (DFCRB1) 0.00 250.00 r
library hold time 0.07 250.07
data required time 250.07
-----------------------------------------------------------
data required time 250.07
data arrival time -1.34
-----------------------------------------------------------
slack (VIOLATED) -248.73
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~

The definition of slack is "data required time - data arrival time".
Why the slack is -248.73? It should be 248.73!

Can anyone explan this case?

Click to expand...

clock DCLK' (rise edge) 250.00 250.00
clock network delay (ideal) 0.00 250.00
ADC_SEL_tmp_reg/CP (DFCRB1) 0.00 250.00 r
library hold time 0.07 250.07
data required time 250.07

Click to expand...