HI,
when I do gatelevel sim, I still use macro behavioral code .I think the code of macro have time information ,and can be used in gate sim.
my macro are RAM, ROM, PLL.
Spice backannotation may be too slow. The popular flow is to extract parasitics after IP merging to obtain a SPEF file. And then by using an advanced timing delay calculator, a SDF file can be generated for your post-layout simulation.
>Spice backannotation may be too slow. The popular flow is to extract >parasitics after IP merging to obtain a SPEF file. And then by using an >advanced timing delay calculator, a SDF file can be generated for your >post-layout simulation.
>Complement for linuxluo's gatelevel simulation.
But I think this is very strange.
I write behavior code for my macro.
I want to SDF to backannotation to behavior code??
A sram macro is nothing but a behavior with specify block for timing annotation . If you can characherize your macro cell , simply backannotate the timing into your own specify block . The corner case have much wide timing span ( as high as twice ) . Dont expect too much the precision in your simulation .
Hi, zackwang
the behavior code I mention is provided by foundry,not your design. And in it ,including detail timing information. So don't use sdf backannotation for this code.