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FIFO does not have address input, it takes care of that on its own. It has counters(gray usually) for address generation.
memory has the address input.
But it has an adress that is generated internally. Is not it? So FIFO also has addresses as other memories. Hence it is wrong to say that FIFO does not have address. What is the difference between the addresses of SRAM and addres of a FIFO? Is it that we can change the address of a SRAM at any order, but for a FIFO it will be incrementing in a regular way and we cannot address a FIFO in any order?
---------- Post added at 13:50 ---------- Previous post was at 13:46 ----------
Another question I have for FIFO. I saw a FIFO architecture that shows a Dual port RAM as the storage element in a document. In another document I found FIFO storage elements are rows of Flipflops with each row containing Flipflops. How many architecture of FIFO is possible? Do u have any document that writes about architectures of FIFO?
There are different types of implementation.. if the fifo is used e.g UART the address is used by the manufacturer and is not exposed to user... the user just enables the FIFO registers and use it... but if you use linked list or array then you have the address pointer and can use it.....
But it has an adress that is generated internally. Is not it? So FIFO also has addresses as other memories. Hence it is wrong to say that FIFO does not have address. What is the difference between the addresses of SRAM and addres of a FIFO? Is it that we can change the address of a SRAM at any order, but for a FIFO it will be incrementing in a regular way and we cannot address a FIFO in any order?
Since the FIFO logic can only be used in conjunction with the memory block, there is no separate FIFO controller macro. As with the RAM blocks, the nomenclature does not refer to a possible aspect ratio, but rather to the deepest possible data depth and the widest possible data width. The FIFO 4k can be configured into the following aspect ratios: 4,096x1, 2,048x2, 1,024x4, 512x9, and 256x18. In addition to being fully synchronous, the FIFO4K also has the following features:
• Four FIFO flags: Empty, Full, Almost-Empty, and Almost-Full
• EMPTY flag is synchronized to the read clock
• FULL flag is synchronized to the write clock
• Both Almost-Empty and Almost-Full flags have programmable thresholds
• Active low asynchronous reset
• Active low block enable
• Active low write enable
• Active high read enable
• Ability to configure the FIFO to either stop counting after the empty or full states are reached or to
allow the FIFO counters to continue
• Designer software will automatically facilitate falling-edge clocks by bubble pushing the inversion
to previous stages.
The FIFOs maintain a separate read and write address. Whenever the difference between the write address and the read address is greater than or equal to the almost-full value (AFVAL), the Almost-Full flag is asserted. Similarly, the Almost-Empty flag is asserted whenever the difference between the write address and read address is less than or equal to the almost-empty value (AEVAL).
Due to synchronization between the read and write clocks, the Empty flag will de-assert after the second read clock edge from the point that the write enable asserts. However, since the Empty flag is synchronized to the read clock, it will assert after the read clock reads the last data in the FIFO. Also, since the Full flag is dependent on the actual hardware configuration, it will assert when the actual physical implementation of the FIFO is full.
For example, when a user configures a 128x18 FIFO, the actual physical implementation will be a 256x18 FIFO element. Since the actual implementation is 256x18, the Full flag will not trigger until the 256x18 FIFO is full, even though a 128x18 FIFO was requested. For this example, the Almost-Full flag can be used instead of the Full flag to signal when the 128th data word is reached. In order to accommodate different aspect ratios, the almost-full and almost-empty values are expressed in terms of data bits instead of data words. SmartGen translates the user’s input, expressed in data words, into data bits internally. SmartGen will allow the user to select the thresholds for the Almost-Empty and
Almost-Full flags, in terms of either the read data words or the write data words, and make the appropriate conversions for each flag. After the empty or full states are reached, the FIFO can be configured so the FIFO counters either stop or continue counting.
Another question I have for FIFO. I saw a FIFO architecture that shows a Dual port RAM as the storage element in a document. In another document I found FIFO storage elements are rows of Flipflops with each row containing Flipflops. How many architecture of FIFO is possible? Do u have any document that writes about architectures of FIFO?
The document talks of Fall through FIFOs and also Dual port RAM FIFOs.
However I was talking of a FIFO consisting of rows of Flipflops with each row containing Flipflops. This I wrote after hearing this from a designer who designed such a FIFO. But I do not know whether this Fall through FIFOs in this document is the same FIFO as I heard about " FIFO consisting of rows of Flipflops with each row containing Flipflops". What do you think?
you are asking like if the knife is made of metal or ceramic. Knife can be made of metal or ceramic or even wood.
FIFO is just a storage and can be made of any types of storage elements.
What can the FIFO is generally made of? Please let me know. I know it can be made using a Dual port RAM. What else can the FIFO be made of? Please let me know.
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