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a question of simulation with Modelsim

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brianhe

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I run simulation in batch mode with Modelsim and the source code is verilog.
On some conditon, I use "examine top/sub1/subx/signal1(3:0)" to capture the lowest 4bits value of signal1(63:0) and output it to a file .
But every time I got all the 64bits, that is not I want.

How can I do and who can help me?
Thanks
 

Looks like a bug to me. Report it to Mentor.
 

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