i think its for a column called multibit cell
In the report, the columns are abbreviated as follows:
* MB—multibit cell
* AR—asynchronous reset
* AS—asynchronous set
* SR—synchronous reset
* SS—synchronous set
* ST—synchronous toggle
Added after 52 minutes:
Multibit Benefits
Multibit inference allows you to map registers, multiplexers, and three-state cells to regularly structured logic or multibit library cells. Multibit library cells (the macrocells, such as a 16-bit banked flip-flop, in the library) have these advantages:
* Smaller area and delay, due to shared transistors (as in select or set/reset logic) and optimized transistor-level layout
* Reduced clock skew in sequential gates, because the clock paths are balanced internally in the hard macro implementing the multibit component
* Lower power consumption by the clock in sequential banked components, due to reduced capacitance driven by the clock net
* Better performance, due to the optimized layout within the multibit component
* Improved regular layout of the datapath
To generate a list of all multibit cells in the design, use the Design Compiler object multibit in a find command, such as
find (multibit, "*")