A question about the report of DC elaboration

[chenzhao.ee]

The following is some information about DC elaborate:
Inferred memory devices in process
in routine rst_launch line 43 in file
'/home/kzmei/multicore_synthesis/multicore_syn/interface/rst_launch.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| cnt_reg | Flip-flop | 7 | Y | N | N | Y | N | N | N |
| cnt_reg | Flip-flop | 7 | Y | N | Y | N | N | N | N |
===============================================================================

What does the MB represent? I think it may be a pin name of Flip-flop,but don't know the exact meaning about it.

 

[sree205]

i think its for a column called multibit cell

In the report, the columns are abbreviated as follows:

* MB—multibit cell

* AR—asynchronous reset

* AS—asynchronous set

* SR—synchronous reset

* SS—synchronous set

* ST—synchronous toggle

Added after 52 minutes:

Multibit Benefits

Multibit inference allows you to map registers, multiplexers, and three-state cells to regularly structured logic or multibit library cells. Multibit library cells (the macrocells, such as a 16-bit banked flip-flop, in the library) have these advantages:

* Smaller area and delay, due to shared transistors (as in select or set/reset logic) and optimized transistor-level layout

* Reduced clock skew in sequential gates, because the clock paths are balanced internally in the hard macro implementing the multibit component

* Lower power consumption by the clock in sequential banked components, due to reduced capacitance driven by the clock net

* Better performance, due to the optimized layout within the multibit component

* Improved regular layout of the datapath


To generate a list of all multibit cells in the design, use the Design Compiler object multibit in a find command, such as
find (multibit, "*")