A question about the pipeline!

[jfzhan]

pipeline combination circuit

Dear all,
I have a question about the pipeline design. As we know, the pipeline is for speeding the circuit. If the delay of combination circiut between two register can not satisfy with the clock cycle width. The compination will be divided and register will be inserted.
Now I wonder, if there are a algorithm such as A+B+C+D+E+F+G+H,
I can design like this,
four register is for storing T1 = A+B , T2 = C+D, T3= E+F and T4= G+H.
and two register is for T11 = T1+T2, T12 =T3+T4,
and so on.

Another method is that I do combination circuit A+B+C+D+E+F+G+H directly.

My question is,

HOW can I know , which method is used based the clock frequency?

for example,
Maybe there are some rules, that if the clock frequency is under 30MHz, you can use second. Otherwise you need conside the first?

 

[masai_mara]

You basically start wihtout a pipeline to gradually introduce the pipeline stages where there are speed bottlenecks. But its good practice to have stages between different alogorithms irrespective of your speed requirement unless you want to avoid latency.

 

[JesseKing]

What do you mean by "which method IS used based the clock frequency"?
did you mean "which method should be used when writing rtl", or you meant "which method the synthesis tool will use to generate netlist"??

 

[adap]

Hi jfzhan,

The higher the frequency the more registers you need to use.
When I wrote RTL for 100Hz I used registers beteween three or four stages. So in your example you can do the combination circuit A+B+C+D+E+F+G+H directly and register the output before use.
For 150Hz I used registers between two or three stages depending the complexity of the circuit. In your example you can do the combination circuit A+B+C+D and register the output T1, then the E+F+G+H and register the output T2 and the T1+T2 can be unregistered or registered depending on the logic that will be used afterwards.

 

[Sparc]

It depends on ur Max Frequency requirement & resources u want to give for.
For A+B+C+D+E+F+G+H= 7 adders, Max Freq= 1/Taddr, Latency =7.
I assume u hv Registers after Adders.
If u want to do it like as u said:
four register is for storing T1 = A+B , T2 = C+D, T3= E+F and T4= G+H.
and two register is for T11 = T1+T2, T12 =T3+T4,
Then T1, T2, T3, T4 can be parallel, and so can be T11 & T12
uses 7 adders, Max Freq will be same but Latency drops to 3.
Now u can decide urself. What i mean to say is there is no such rule, but one can himself set his rules to architect the design as according to the requirements of the system.

 

[jfzhan]

Thanks every one for good answer!

The mainly purpose is that if I use too much pipeline in RTL design, The gate count will be larger than that of no pipeline.

Thanks!!!

 

[funzero]

tool can decide whether to use pipeline . How you describe the circuit . the tools implement acrodingliy.

 

[jfzhan]

My work flow is ,

1 decide the algorithm
2 decide the architecure and decide the pipeline
3 write the RTL
4 synthesis
5 if the delay can not be satisified, redesign.

I don't know which tools can help to decide the pipeline?

 

[sunms]

yes,it's up to you to decide the pipeline!
Tools may be helpful,but you can't rely on it.

 

[zyphor]

Hi,

I think at first you should know about the algorithm's complexity. If all is simple algorithm you need not pipleline. You must optimize your algorithm and find the total logic stages your algorithm need, then based on clock frequency and process, you can find how many clock period you need to complete the algorithm, and then you can use pipleline techniques.

 

[rlogin]

as for you case, the most quick way is to
use dc retiming when you defined the stages

 

[power-twq]

yes, if your system operating frequency is low,

you can use second method.

if your system operating frequency is very high,

perhaps, you can use first method.

Dear all,
I have a question about the pipeline design. As we know, the pipeline is for speeding the circuit. If the delay of combination circiut between two register can not satisfy with the clock cycle width. The compination will be divided and register will be inserted.
Now I wonder, if there are a algorithm such as A+B+C+D+E+F+G+H,
I can design like this,
four register is for storing T1 = A+B , T2 = C+D, T3= E+F and T4= G+H.
and two register is for T11 = T1+T2, T12 =T3+T4,
and so on.

Another method is that I do combination circuit A+B+C+D+E+F+G+H directly.

My question is,

HOW can I know , which method is used based the clock frequency?

for example,
Maybe there are some rules, that if the clock frequency is under 30MHz, you can use second. Otherwise you need conside the first?