Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

A problem about transistor simulation using nanosim .

Not open for further replies.


Junior Member level 2
Jul 1, 2005
Reaction score
Trophy points
Activity points
Hello ,all

I met with a problem when i try to do transistor level simulation using nanosim ,it puzzled me for several days . I hope someone may help me out .

I write a very simple 4-bit full adder in verilog , and I synthesis with Synopsys DC adn get a verilog netlist .
I simulate verilog code using Synopsys vcs , and get a VCD file . I translate the VCD file into vector stimulus using vcd2vec command . and , i want to use this vector file as the stimulus for the spice netlist .

I translate verilog-netlist into spice netlist using nettran in Hercules .

Then I start nanosim , input the spice netlist and vector file , then the problem come out .

First : When I click on the Hierarchy Explorer in nanosim , I only can see the top , I cant see any structure .

Second : when i simulate , it tells me that , the vector file doesn't connect to any node of the netlist .

but , I'm sure that the signal names in the vector file are identical with that in the spice netlist .

Then how can I bind the two ?

Third : the waveform only display the input signals in the vector files and all the output signals are dangling , adn set to 0V.

can anyone give me some hints?

thx very much in advance ! bow ~

Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com