a problem about S/H circuit

[winsonpku]

now,i am designing a S/H circuit,which is used in the 14-bit pipeline ADC.then i want to know if the S/H circuit's resoluation is about 0.03mv,does it mean that:all the parameters in the circuit is at the accuracy level.for example,the AMP's output CM voltage,the sampling,the swtich's charge injection or clock feedthrough must be at the accuracy level.
another question is how to test the S/H circuit's resolution,i mean when i simuate the circuit by Hspice and how i debug the circuit when the accuarcy is lower than the specification.
any advice is welcom! thanks

 

[noiseless]

i believe the accuracy is not a problem. what should be concerned is mismatching

as to the simulation, can you do the transient simu, then do the fft?

 

[winsonpku]

what's the meaning of "i believe the accuracy is not a problem. what should be concerned is mismatching",you mean the accuracy can be easy to get?!
i have do the transient simu,the function seems right,but the accuracy seems not so good.because i found the resolution was about 1~2mv,but not the 0.03mv
and how to do the fft?can you tell me the details?
thanks first!

i believe the accuracy is not a problem. what should be concerned is mismatching

as to the simulation, can you do the transient simu, then do the fft?

 

[ezt]

Hi.
Because the S/H is the first stage, so it should have 14 bits accuracy. But usually we don't calculate this accuracy for each part of the stage such as switches. Instead we can calculate the ess (steady-state error) for the whole stage and it should be at least 1/2^14. But if you want to desig na really good ADC, that's better always to design a more accurate stage in order to have the appropriate accuracy in all process and temperature corners. You can simply calculate ess by applying a step input (pulse input with large period) and watching the output transient response.
For FFT, you can peak up output voltage samples (by using .tran statement in HSpice) and use this data in MATLAB® to find SNDR, SFDR and other dynamic specifications. But be careful in using FFT function. e.g. you want to do a 31/64 FFT (Nyquist rate) on your output signal. You MUST set the input freq in simulator to (31/64 * fs), where fs is the sampling freq. and you MUST let the transient response at least pass 64*Ts, where Ts is sampling period (i.e. 1/fs).

Regards,
EZT

 

[watersky]

Because pipeline is used, S/H of the first stage must have the accuracy of 14 bits. if the differential structure is used, the accuracy can be widened double. but i think it is difficult if a better S/H is not used. ADI can produce 24 bits ADC, I wonder whether the especial S/H structure is used? if you konw, please tell me. thanks!

 

[arsenal]

anyone can help me setup the simulation schematic to measure the accuracy of a s/h circuit?
thanks

 

[noiseless]

no process can produce 14 bit accuracy components. however, matching can be better than accuracy. As far as I know, the resolution of the pipelined ADC is limited by the mismatch. I have no idea how Aanlog device can produce 24bits ADC. I guess they using calibration or other algorithm at the end of the ADC

 

[winsonpku]

but you kown that the cmfb of the amp is sc cmfb,so how can i do the step response simulation?

Hi.
Because the S/H is the first stage, so it should have 14 bits accuracy. But usually we don't calculate this accuracy for each part of the stage such as switches. Instead we can calculate the ess (steady-state error) for the whole stage and it should be at least 1/2^14. But if you want to desig na really good ADC, that's better always to design a more accurate stage in order to have the appropriate accuracy in all process and temperature corners. You can simply calculate ess by applying a step input (pulse input with large period) and watching the output transient response.
For FFT, you can peak up output voltage samples (by using .tran statement in HSpice) and use this data in MATLAB® to find SNDR, SFDR and other dynamic specifications. But be careful in using FFT function. e.g. you want to do a 31/64 FFT (Nyquist rate) on your output signal. You MUST set the input freq in simulator to (31/64 * fs), where fs is the sampling freq. and you MUST let the transient response at least pass 64*Ts, where Ts is sampling period (i.e. 1/fs).

Regards,
EZT

 

[ezt]

Dear winsonpku,
You use SC-CMFB, so in one clock phase the circuit samples and in the other phase it holds the last data in sampling phase. So you can give a step input to your circuit and check the output in holding phase (or sometimes called amplifying phase according to your application). In holding phase your output should settle whithin the required time with the required accuracy (i.e. with less than 1/2^14 * VFS voltage error, where VFS is here the amplitude of your step if the gain of your SHA is unity).
Good luck.

Regards,
EZT

 

[watersky]

use an adeal DAC, input is from 0 to max,which is step by step. They are ideal step voltage you need.

 

[ocarnu]

Unfortunatelly, you cannot simulate the accuracy. In mainly depends of mismatch in input transitors, swtches, charge injection. And it decisively depends on layout. This is why simlated results have no value and you cannot publish them in any decent paper, journal, or conference. Otherwise, is full out there of undergrad projects with amaizing results.
The best you can do: det the mismatch data from the foundry and size the trasistors accordingly.

 

[watersky]

I think switches are first resolved. It also depend on voltage sampled. The calibration must be used in ADC, which calibrate the results. But I don't know the calibration is for sampling and transform or for only transform.