hi,
my 2cents,
DC is a very matured tool, there for decades , seen tons of proven success of plenty of tapeouts to its data points .
few technical inputs
*Tool can break combinational loops and go ahead, it will saying in the warning that loop is there.
*multi mode scenarios can be performed.
* if muxes select lines is not constrained then it will optimize both the paths, so ideally constraining select lines is not a choice. if we want to remove unwanted paths, and means to reduce runtime then we can do so.
* tools are capable of plenty of logic optimization, register re-timing/constant propagation/register merging.
* clock-gating as mentioned earlier is a design strategy to have a single clock-gating cell based on latch based, to avoid glitches, and tools are strong enough , to optimize multiple clock-gating cells.
* Address power issues with UPF(unified power format).
* Tons of scan related optimizations.
* DC-Topo, to address the years old correlation issue of wire-load models.
and a strong handshake with synopsys tools like ICC , power compiler, DFT compiler, design wares,.... address logical/physical constraints to address area/power/timing/co-relation across tools/flows/yield/Test/...
How many tools come cannot come close to full-custom optimization, our Job security is at stake. this prooves humans are one step ahead with machines.
only question is time factor, automation, runtime, parallelism, hierarchical, human capital, we look for alternative which is tools and we need to live in practical world, with multiple projects and way to handle it.
Unfortunately tools are still a long way to go for analog designs.
myprayers,
chip design made easy
https://www.vlsichipdesign.com