5 stage PRBS genrator in 20 bit output sequence

[rocking1234]

Hi

I have a file which will repeat the random number after 31 clock cycle. But problem is I really cant track down how they created the prbs block. I could not decode the logic from the rtl. Could any1 tell me how they got the 20 bit output from the 5 stage prbs. I am attaching the rtl code for the 5 stage prbs.

Any suggestion will be appricitated.

 

[rca]

what are the goal of this module?
it 'seems to be only a xor logic, like CRC...

synthesis tool can drawn you the overall logic, but I don't expect, that help you so much

 

[rocking1234]

The goal of tis module is to generate a 20 bit random number at one clock cycle. It is intended to check the data integrety of the board we gonna design. This module will repeat the random number after 32 clock cycle but I was really confused about the logic how this module gernerate the 20 bit signal for each clcok cycle