module router
// The router location and the width and depth of the FIFO are paramatised
#(parameter xLocation = 0,
parameter yLocation = 0,
parameter FIFO_WIDTH = 64,
parameter FIFO_DEPTH = 4)
// Outputs and inputs
(output logic [FIFO_WIDTH-1:0] routerDataOut [0:4],
output logic [4:0] holdPorts_OUT, writeRequest_OUT,
input logic [FIFO_WIDTH-1:0] routerDataIn [0:4],
input logic [4:0] holdPorts_IN, writeRequest_IN,
input logic reset, clk);
// Internal Logic, essentially this is just connections.
logic [FIFO_WIDTH-1:0] bufferDataOut [0:4];
logic [4:0] outputPortRequest [0:4];
logic [4:0] readRequest;
logic [2:0] sel [0:4];
// Generate 5 input units
genvar j;
generate
for ( j = 0; j< 5; j++ )
inputUnit #(xLocation, yLocation, FIFO_WIDTH, FIFO_DEPTH) inputUnitj (bufferDataOut[j], outputPortRequest[j], holdPorts_OUT[j], routerDataIn[j], readRequest[j], writeRequest_IN[j], reset, clk);
endgenerate
// Instantiate switch allocator and switch
switchAllocator switchAllocator (sel, readRequest, writeRequest_OUT, outputPortRequest, holdPorts_IN, reset, clk);
switch #(5,5,FIFO_WIDTH) switch (routerDataOut, bufferDataOut, sel);
endmodule