3D array in SystemVerilog

[BartlebyScrivener]

I have several modules coming together to make a network. At the lowest level I have a buffer giving an output

[63:0] bufferDataOut

which is passed, along with 4 other instantiated buffers to a router module using a for loop and

bufferDataOut[j]

to an array [63:0] bufferDataOut [0:4]

which goes through a switch to create

[63:0] routerDataOut [0:4]

I want to send this, along with other routers, to a network module, using a for loop to instantiate, to fit in an array

[63:0] networkData [0:4] [0:Number of Routers]

any ideas how I would do this please?

I tried using networkData in a loop in the port space when instantiating but it throws up errors when trying to simulate claiming the Array ranges [0:number of routers] & [0:4] have different lengths.

So I tried using networkData[0:4] in the loop in the port space and when trying to compile this throws up the error near "[": syntax error, unexpected '[', expecting ')'

So I tried using networkData[0:4] in the loop in the port space and this throws the error Illegal output or inout port connection for "port 'routerDataOut'" when trying to simulate.

Any help is greatly appreciated!

 

[mrflibble]

Couple of quick notes...

Best to post your code here, using

 tags. Also, without seeing your code ... look into using a "generate" statement instead of loop. Sometimes that's easier, a bit depending... And regarding error, please copy/paste the exact error from the synthesis report. Otherwise we're just guessing here. :P

 

[BartlebyScrivener]

Ok thanks. I will post up both modules I am using now. The router module is working if loaded on its own in a testbench. I have been chasing signals round it all day. Test bench seriously affects the eyes, staring at all those lines lol.

module router
  
  // The router location and the width and depth of the FIFO are paramatised
  
  #(parameter xLocation = 0,
    parameter yLocation = 0,
    parameter FIFO_WIDTH = 64,
    parameter FIFO_DEPTH = 4)
    
    
    // Outputs and inputs
    
    (output logic [FIFO_WIDTH-1:0] routerDataOut [0:4],
     output logic [4:0] holdPorts_OUT, writeRequest_OUT,
      input logic [FIFO_WIDTH-1:0] routerDataIn [0:4],
      input logic [4:0] holdPorts_IN, writeRequest_IN,
      input logic reset, clk);
  
   
    // Internal Logic, essentially this is just connections.
    
    logic [FIFO_WIDTH-1:0] bufferDataOut [0:4];
    logic [4:0] outputPortRequest [0:4];
    logic [4:0] readRequest;
    logic [2:0] sel [0:4];
    
   
    // Generate 5 input units
  
    genvar j;
    generate 
      for ( j = 0; j< 5; j++ )
        inputUnit #(xLocation, yLocation, FIFO_WIDTH, FIFO_DEPTH) inputUnitj (bufferDataOut[j], outputPortRequest[j], holdPorts_OUT[j], routerDataIn[j], readRequest[j], writeRequest_IN[j], reset, clk);
    endgenerate
    
    
    // Instantiate switch allocator and switch
    
    switchAllocator switchAllocator (sel, readRequest, writeRequest_OUT, outputPortRequest, holdPorts_IN, reset, clk);
    switch #(5,5,FIFO_WIDTH) switch (routerDataOut, bufferDataOut, sel);
    
    
endmodule

and ....

module network
  #(parameter X_NODES = 3,
    parameter Y_NODES = 3,
    parameter FIFO_WIDTH = 64,
    parameter FIFO_DEPTH = 4)
    
    (input logic clk);
    
  
  // Internal logic for generating node numbers and x and y location
  
  logic [2:0]  xLocation;
  logic [2:0]  yLocation;
  logic nodeNumber;
  logic k;
  
  
  // Internal logic for storing network data
  
  logic [63:0] networkData             [0:4][0: (X_NODES * Y_NODES)-1];
  logic [63:0] routerInputData         [0:4][0: (X_NODES * Y_NODES)-1];
  logic [4:0]  networkHoldPorts_out    [0: (X_NODES * Y_NODES)-1];
  logic [4:0]  networkHoldPorts_in     [0: (X_NODES * Y_NODES)-1];
  logic [4:0]  networkWriteRequest_out [0: (X_NODES * Y_NODES)-1];
  logic [4:0]  networkWriteRequest_in  [0: (X_NODES * Y_NODES)-1]; 
  
  
  // Generate router input data using networkData
  
  always_comb
    begin
      for (int nodeNumber = 0; nodeNumber < (X_NODES*Y_NODES); nodeNumber++)
        begin
          routerInputData[0][nodeNumber] = (nodeNumber < ((X_NODES-1)*Y_NODES)) ? networkData [2][nodeNumber + X_NODES] : 'b0;
          routerInputData[1][nodeNumber] = ((nodeNumber + 1) % X_NODES)         ? networkData [3][nodeNumber + 1]       : 'b0;
          routerInputData[2][nodeNumber] = (nodeNumber > X_NODES)               ? networkData [0][nodeNumber - X_NODES] : 'b0;
          routerInputData[3][nodeNumber] = (nodeNumber % X_NODES)               ? networkData [1][nodeNumber -1]        : 'b0;
          routerInputData[4][nodeNumber] = 'b0;
        end
    end
  
  
  // Generate 2D Mesh
  
  genvar x,y;
    generate 
      for ( y = 0; y < Y_NODES; y++)
        begin
          for ( x = 0; x < X_NODES; x++)
            begin
              assign k = x+(X_NODES*y);
              router #(x, y, FIFO_WIDTH, FIFO_DEPTH) routerxy (networkData[k][0:4], networkHoldPorts_out[k], networkWriteRequest_out[k], routerInputData[k][0:4], networkHoldPorts_in[k], networkWriteRequest_in[k], reset, clk);
            end
        end
      endgenerate
        
endmodule

and the error I am getting is

# ** Error: (vsim-3053) C:/altera/11.0/network.sv(52): Illegal output or inout port connection for "port 'routerDataOut'".
#         Region: /testData/networkTest/genblk1[2]/genblk1[4]/routerxy
# ** Error: (vsim-3053) C:/altera/11.0/network.sv(52): Illegal output or inout port connection for "port 'holdPorts_OUT'".
#         Region: /testData/networkTest/genblk1[2]/genblk1[4]/routerxy
# ** Error: (vsim-3053) C:/altera/11.0/network.sv(52): Illegal output or inout port connection for "port 'writeRequest_OUT'".
#         Region: /testData/networkTest/genblk1[2]/genblk1[4]/routerxy

Repeated again and again. I am using SystemVerilog with a free tool off the internet called ModelSim. I am guessing it is something silly as this is the first thing I have written, it has been kind of a steep learning curve. Thanks for your help.