20ms waveform with 10% duty cycle

[oddworld]

Hello all, I am currently using VHDL to program a Nexys2 board with Spartan 3E FPGA.

I am trying to produce an output signal that has a 20ms period with a 1-2ms duty cycle. I want to be able to adjust the duty cycle within this 1-2ms range using buttons.

The clock frequency on the board is 50MHz. How can I do this and be able to view the result with an oscilloscope?

 

[sudhirkv]

you can use counter for it. since u use 50mhz clock, one clock pulse will have 20 ns second. you can design a counter which will toggle when the counter reaches 100000(decimal) and 1000000(decimal).

How many buttons u have in u r board?.

 

[oddworld]

The board has four buttons, I will be using one to reset the duty cycle to 1.5ms (neutral) and two for increase/decrease duty cycle within the 1-2ms range. I have been trying to use a counter, the problem arises when the counter reaches the period since it is counting in binary. I tried to simply set the counter to all 1s once it reached the period so it would overflow on the next clock cycle, but it doesn't seem to have worked. Is there anything special about comparing signal values in VHDL?

 

[sudhirkv]

are you taking care of switch debouncing?. is it like you have added the switch or the switch is already in the board?. If its already in the board then there is no problem. or else u need to take care of switch debouncing.

is it one step increase or many steps?

let say if you press the button will it increase every time when you press the button?.