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How to stop simulation in VHDL testbench?

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bigdog

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Hello,

I don't know how to stop my simulation, my testbench is described in VHDL and I use ncsim, is there any method to stop the simulation just like using $stop, $finish in Verilog?

Regards,
 

Hi,

You can write at the end of your testbench:

assert false report "end of simulation" severity failure;


Devas
 
Hello Devas,

Yes, the statement works!

Thanks a lot!

Regards,
 

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