Measure the time period between 2 signals

I want to measure th etime period between two signals ( rst and cs )
my FPGA is connected to push button switch (sw) to initialize the counter with zero and also connected to 7 segment to display the results
My design uses a counter signal ranges fro 0 to 1048580
--------------
my code is below :
--------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

Entity COUNT is
port(
sw : in std_logic ;
rst : in std_logic ;
clk : in std_logic ;
cs : in std_logic ;
a : out std_logic;
b : out std_logic;
c : out std_logic;
d : out std_logic ;
e : out std_logic ;
f : out std_logic ;
g : out std_logic
);
end COUNT;

architecture a of COUNT is

signal counter : integer range 0 to 1048580;
signal decide : std_logic_vector(1 downto 0);

begin

stsprocess(clk,sw,decide)
begin

if clk='1' and clk'event then
if sw = '0' then
decide <= "00" ;
else

case decide is
when "00" =>
counter <= 0 ;
a <= '0' ; --------------- H
b <= '1' ;
c <= '1' ;
d <= '0' ;
e <= '1' ;
f <= '1' ;
g <= '1' ;
decide <= "01" ;
when "01" =>
if ( rst = '1' and cs = '1' ) then
decide <= "10" ;
else
decide <= "01";
end if;
when "10" =>
if ( rst = '1' and cs = '0' ) then
decide <= "11" ;
elsif ( rst = '1' and cs = '1' ) then
if (counter >1048576 ) then
counter <= counter ;
else
counter <= counter +1 ;
end if ;

else
-- U
a <= '0' ;
b <= '1' ;
c <= '1' ;
d <= '1' ;
e <= '1' ;
f <= '1' ;
g <= '0' ;
End if ;
when "11" =>
if (counter <= 104857 and counter > 0)then -- 0
a <= '1' ;
b <= '1' ;
c <= '1' ;
d <= '1' ;
e <= '1' ;
f <= '1' ;
g <= '0' ;
----------
elsif (counter <= 209715 and counter > 104857 )then -- 1
a <= '0' ;
b <= '1' ;
c <= '1' ;
d <= '0' ;
e <= '0' ;
f <= '0' ;
g <= '0' ;
--------
elsif (counter <= 314572 and counter > 209715)then -- 2
a <= '1' ;
b <= '1' ;
c <= '0' ;
d <= '1' ;
e <= '1' ;
f <= '0' ;
g <= '1' ;
----------
elsif (counter <= 419430 and counter > 314572 )then -- 3
a <= '1' ;
b <= '1' ;
c <= '1' ;
d <= '1' ;
e <= '0' ;
f <= '0' ;
g <= '1' ;
----------
elsif (counter <= 524288 and counter > 419430)then -- 4
a <= '0' ;
b <= '1' ;
c <= '1' ;
d <= '0' ;
e <= '0' ;
f <= '1' ;
g <= '1' ;
----------
elsif (counter <= 629145 and counter > 524288 )then -- 5
a <= '1' ;
b <= '0' ;
c <= '1' ;
d <= '1' ;
e <= '0' ;
f <= '1' ;
g <= '1' ;
----------
elsif (counter <= 734003 and counter > 629145 )then -- 6
a <= '1' ;
b <= '0' ;
c <= '1' ;
d <= '1' ;
e <= '1' ;
f <= '1' ;
g <= '1' ;
----------
elsif (counter <= 838860 and counter > 734003 )then -- 7
a <= '1' ;
b <= '1' ;
c <= '1' ;
d <= '0' ;
e <= '0' ;
f <= '0' ;
g <= '0' ;
----------
elsif (counter <= 943718 and counter > 838860 )then -- 8
a <= '1' ;
b <= '1' ;
c <= '1' ;
d <= '1' ;
e <= '1' ;
f <= '1' ;
g <= '1' ;
----------
elsif (counter <= 1048576 and counter >943718 )then -- 9
a <= '1' ;
b <= '1' ;
c <= '1' ;
d <= '1' ;
e <= '0' ;
f <= '1' ;
g <= '1' ;
else -- E
a <= '1' ;
b <= '0' ;
c <= '0' ;
d <= '1' ;
e <= '1' ;
f <= '1' ;
g <= '1' ;
----------
end if;
when others => -- U
a <= '0' ;
b <= '1' ;
c <= '1' ;
d <= '1' ;
e <= '1' ;
f <= '1' ;
g <= '0' ;
end case;
end if ;
end if;
end process;

end;


-------------

Can any body test this code and tell my why it didn't work

I have attached the discription graph and 7 segment indications !!

Hi,

Your design seems to work ...
But after the first display of the counter value, the only way to restart the count is to set sw to 0. If not, your state machine "decide" will stay at 11 state.
To help you in debugging, draw your state machine and check that you did not forget any transition between states, and that all states are defined.

At last, if I had to design this function, I'll make several process to separate the functions : 1 for the state machine, 1 for the counter, 1 for the display. I would also use a divided clock in order to symplify the combinatory logic after synthesis for the display conditions.

I hope this will help you.


:wink:

Thanks r_e_m_y ,
Actually I wanted the process to be executed one time so I made it
depend on the SW press
Also I have solved the problem , As you said there were no any
problems in the simulator but the problem was that the i/p signals
has some hazards ! i saw it using logic analyzer
I have solved it by enter the i/p signals to shift register and
anding all shift register outputs to make sure that the change
is due to a real change not due to hazards !
and It works correctly :lol: