bigdog
Junior Member level 2
Hello,
I don't know how to stop my simulation, my testbench is described in VHDL and I use ncsim, is there any method to stop the simulation just like using $stop, $finish in Verilog?
Regards,
I don't know how to stop my simulation, my testbench is described in VHDL and I use ncsim, is there any method to stop the simulation just like using $stop, $finish in Verilog?
Regards,