a problem in pre-simulation with annotating sdf

sdfnl1

Hi, all.
I have some probem in pre-simulation. When i simulate the gate-netlist with no sdf information, the waveform is OK, but when i simulate the gate-netlist with sdf annotation, the clock signal wave is wrong ( for example, dem_clk is one of clock signal in my design ,and it's slower than my expected. Observed from the waveform, dem_clk is 8MHz in the simulation with no sdf annotation ,but dem_clk is only much slower than 8MHz in the simulation with sdf annotation) , and i have found that when i run pre-simulation with sdf annotation there are some warning in ncverilog log file. it indicate some negative timing value in the sdf file.
I give the warning as follows, please give me some advise.
thank advance!

PS1 warning in DC log file for clock signal and reset signal)
write_sdf active_design +"_syn.sdf"
Information: Annotated 'cell' delays are assumed to include load delay. (UID-282)
Information: Updating design information... (UID-85)
:!:Warning: Design 'blue_modem' contains 2 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
Information: Writing timing information to file '/export/user/jinruan/project2005/bluemodem/V2.0/syn/blue_modem_syn.sdf'. (WT-3):?: ( one of the 2 high-fanout nets is dem_clk signal)
PS2: (warning in ncverilog log file)
:!:ncelab: *W,SDFNL1 (/export/user/jinruan/project2005/bluemodem/V2.0/lib/csm25.v,19189|12): Attempt to annotate a negative value to a 1 limit timing check in instance (test_blue_modem.BLUEMODEM.BLUEDEM.IFIR.GFTROM6.dout_reg_20), setting to 0 </export/user/jinruan/project2005/bluemodem/V2.0/syn/blue_modem_syn.sdf, line 460649>.
$recovery(posedge RN, posedge CK, trec$RN, NOTIFIER);

sdf annotate posedge

i

t's slower than my expected

Click to expand...

what u mean by slower than expected?
have u used set_dont_touch_network on dem_clk while synthesis??

ncverilog+sdf warning+negative

the clock signal should be set with set_dont_touch_network attribute to keep it untouched in the synthesis. That's one thing. But it seems that even buffers are inserted to your clock in the synthesis your clock frequency will be unchange.

If you could describe it case in detail, we could help you.

- You clock is adding in testbench which is 8M. Where did you observe it became much "slower" (e.g. to 7M)? At the CK pin of the DFF? At the input of your design? or Some node other than above?

sdf annotation log no numbers

Hi jinruan,

I see that you are still struggling with post-synthesis simulation.

I can guess the following from the log file:

> PS1.
You have at least one high fan-out net (more than 1000) in your design. You do not create a buffer tree for the high fan-out net, which is correct. However, if you are going to generate a sdf at this point, the gate driving the high fan-out net is going to be very very slow. If the high fan-out net is the clock, the hugh clock slew will make the FF delay very very slow. You can:

1. tell the tool that the high fanout net is "ideal net". Can do this in Ambit, but not sure if this can be done in DC. Anyone can enlighten us?

2. go ahead to synthesis the high fan-out net (i.e. do not set dont-touch-net). However, the netlist is then good for simulation, but not so good for P&R. May run into problem like clock skew (if the high fan-out net is clock)

3. edit the sdf file. Change the delay of the clock driver and the delay of the high fanout net.


> PS2
There is a negative setup or hold check. New version of SDF synthax will not accept negative setup and hold check, and will zero out the value.


Regards,
Eng Han

netlist sdf problems

Hi Han,
I have set_dont_touch attribute to "dem_clk" and "clk" "rst_n", "dem_clk" "clk" are the generated clock in my design , and "rst_n" is the generated reset signal in the design. I have look up the violation report that "clk" and "rst_n" are the high-fanout nets. the following are the violations:
PS1:
max_transition

Required Actual
Net Transition Transition Slack
-----------------------------------------------------------------
rst_n (dont_touch) 4.50 394.25 -389.75 (VIOLATED)


max_capacitance

Required Actual
Net Capacitance Capacitance Slack
-----------------------------------------------------------------
rst_n (dont_touch) 6.24 1012.00 -1005.76 (VIOLATED)
clk (dont_touch) 6.24 7.63 -1.39 (VIOLATED)

and i have checked the .sdf file and find that timing delay value of "rst_n" and "clk"
is more than 50( it's so bigger).

PS2: i have some doubt as follow:
1) "dem_clk" , "clk" both are the generated clock, and i have set the same attributed to them, and they both drive many DFF, why "clk" have design rule violaiton but "dem_clk" isn't that case ?
2)when simulation, "dem_clk" is much slower than 8MHz, i have checked the waveform that "dem_clk" is about 250KHz(why? where does it came from?)

simulation sdf wrong

Hi Jinruan,

I think you know what is going on for "PS1".

For "PS2", I cannot think of a reason. I suggest you trace the waveform from the input of of the generated clock to the output of the generated clock. Should be able to find out the root cause in this way,


Regards,
Eng Han

attempt to annotate negative

PS2: (warning in ncverilog log file)
:!:ncelab: *W,SDFNL1 (/export/user/jinruan/project2005/bluemodem/V2.0/lib/csm25.v,19189|12): Attempt to annotate a negative value to a 1 limit timing check in instance (test_blue_modem.BLUEMODEM.BLUEDEM.IFIR.GFTROM6.dout_reg_20), setting to 0 </export/user/jinruan/project2005/bluemodem/V2.0/syn/blue_modem_syn.sdf, line 460649>.
$recovery(posedge RN, posedge CK, trec$RN, NOTIFIER);



For the above problem, plz try to put the same constraints such as i/p delay,clkdelay.....and so on in u r testbench also.