Serdes IP integration to ASIC

Hi all, I am trying to learn the knowledge required to integrate a SERDES IP to an ASIC. (technical aspect with latest tech 7nm). I would like to know the following
1) Apart from the general working of the serdes IP, what are the key aspects to be know to help a customer integrate the IP into their ASICs
2) Similar to first question, but what do an application engineer who helps their clients integrate an IP to their ASIC generally look for (meaning the constraints, the features, requirements). I have no experience in the field, but would like to learn.
3) What basics should we have good knowledge in to get to do the above work. If some1 can reply woud be grt..

preethi19 said:

Hi all, I am trying to learn the knowledge required to integrate a SERDES IP to an ASIC. (technical aspect with latest tech 7nm). I would like to know the following
1) Apart from the general working of the serdes IP, what are the key aspects to be know to help a customer integrate the IP into their ASICs
2) Similar to first question, but what do an application engineer who helps their clients integrate an IP to their ASIC generally look for (meaning the constraints, the features, requirements). I have no experience in the field, but would like to learn.
3) What basics should we have good knowledge in to get to do the above work. If some1 can reply woud be grt..

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All very vague...but at the bare minimum a client wants to know how fast, how power hungry, and how big an IP is. That might require a huge datasheet with all possible operating modes and speeds. On a second level, which metal layers are used internal to the IP. Support for power shut off is also a common requirement/request.

In general for any IP to be integrated in SOC (for instance) require power domain requirements (possibly UPF), clock domain requirements, input/output details and any common standard interface for connectivity. Also most SOCs require certain level of quality for the IP they are integrating. Different companies have different quality requirements.

From backend perspective, if you are providing a hard IP with layout, you will have to give details about metal layers used, congestion information, timing information, power consumption information etc.

Things are variable...

Thanks for the reply guys! Sorry if i am vague, but I am trying to learn the very basics of all this. To start of, it seems like IP can be provided to the customer as a FE design and/or as a hard IP (or does both go hand in hand)??
1) Meaning does Front End get the IP and customize certain features to their requirement at the RTL level and then pass it down to PD???
2) If as hard IP, then what sort of checks would a PD engineer do, to make sure the IP can be integrated into the layout of the SoC??

So if I am an IP vendor and my customer is looking to intergrate my IP to their SoC, then as you mentioned they would start with the power specs, input/output and all the other details of the IP. But I didn't quite understand when you meant "most SoC's require certain level of quality to intergrate an IP".. What qualities are these (again vague), but like in a very general basic requirements.

Secondly as you mentioned about backend perspective, what do you mean by metal layers.. I thought in general all metal layers are used from the std cells to routing ie till M12. Yes the std logic and macros are of lower metal layers (is this what you meant by metal layers??). Also if as a hard IP, can the PD engineer change the util, tile shape of the serdes, or does it always remain fixed in size and shape?

preethi19 said:

Thanks for the reply guys! Sorry if i am vague, but I am trying to learn the very basics of all this. To start of, it seems like IP can be provided to the customer as a FE design and/or as a hard IP (or does both go hand in hand)??

Click to expand...

Yes you can provide the IP as Soft IP and Hard IP.

1) Meaning does Front End get the IP and customize certain features to their requirement at the RTL level and then pass it down to PD???

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In case of Soft IP you can do so. However, Hard IP is like a black box. You cannot change anything inside RTL for Hard IPs.
For hard IP, you get physical design as well from IP provider.

2) If as hard IP, then what sort of checks would a PD engineer do, to make sure the IP can be integrated into the layout of the SoC??

Click to expand...

I am not sure here as I am frontend engineer.

So if I am an IP vendor and my customer is looking to intergrate my IP to their SoC, then as you mentioned they would start with the power specs, input/output and all the other details of the IP. But I didn't quite understand when you meant "most SoC's require certain level of quality to intergrate an IP".. What qualities are these (again vague), but like in a very general basic requirements.

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Generally there are checks that IP providers must adhere to. For example, it should pass CDC checks for a specific version of CDC tool. Other example will be to have lint pass rate to may be close to 100% or provide waivers. For multiple power domain IPs, there are multiple checks to verify if design intent is correct.

Secondly as you mentioned about backend perspective, what do you mean by metal layers.. I thought in general all metal layers are used from the std cells to routing ie till M12. Yes the std logic and macros are of lower metal layers (is this what you meant by metal layers??). Also if as a hard IP, can the PD engineer change the util, tile shape of the serdes, or does it always remain fixed in size and shape?

Click to expand...

Well all metal layers cannot be used for 1 IP. How will SOC level routing happen in that case? SOC layout teams reserves higher metal layers.

Thanks,
Abhishek